Xilinx Virtex-6 FPGA User Manual

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Xilinx Virtex-6 FPGA User Manual Manual pdf 3 page image

UG371 (v2.0) February 16, 2010 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideRevision HistoryThe following table shows the revision history for this document.Date Version Revision09/16/09 1.0 Initial Xilinx release.02/16/10 2.0 Changed the clock domain for the RXPOWERDOWNx[1:0] ports in Table 1-3, page 15, Table 2-10,page 56, and Table 2-12, page 66.Chapter 1: Updated OTU-3 values in Table 1-1. In Table 1-3, renamed DO port to DRPDO andrelocated ports I, IB, and O to new Table 1-4.Chapter 2: In the GTHRESET description in Table 2-7 and Table 2-10, indicated that GTHINIT mustbe pulsed only after GTHRESET is deasserted. In Table 2-10 and Table 2-12, changedRXPOWERDOWN and TXPOWERDOWN descriptions for the x4 link case. Added ReferenceClock Input Structure, page 43. Removed reference to LVDS clocks as being able to drive thereference clock pins, page 44. Added sentence about MMCM and BUFR to TSTREFCLKOUT portdescription in Table 2-4. Added PLL, page 48. Revised Figure 2-12, Figure 2-13, and Figure 2-14. InTable 2-11, changed the meaning of bit code 110 for bits [13:11] and [10:8] of thePCS_MODE_LANE attribute to Reserved; changed the 8B/10B reset value for thePCS_RESET_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizard toattribute PCS_RESET_1_LANE, bits [15:2]. In Table 2-14, added the encoding to thePMA_LPBK_CTRL_LANE attribute description; changed the Reserved bits for [13:11] and [10:8] inthe PCS_MODE_LANE attribute; added reference to the Virtex-6 FPGA GTH Transceiver Wizardto attribute PMA_LPBK_CTRL_LANE, bits [15:2]. In Table 2-15, changed the name of portDO[15:0] to DRPDO[15:0]. Added note about DISABLEDRP to Using the DRP Interface, page 70and Using the Management Interface, page 72.Chapter 3: Added 32 and 64 bits to 8B/10B mode in Table 3-1. Added two rows to 8B/10B Modefor 32-bit and 64-bit fabric interface data width in Table 3-2. Revised manual adjustment modesettings for the BUFFER_CONFIG_LANE attribute in Table 3-4, and changed the meaning of bitcode 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved in Table 3-4,Table 3-6, Table 3-8, and Table 3-10. Added reference to the Virtex-6 FPGA GTH Transceiver Wizardto attribute PCS_RESET_1_LANE, bits [15:2] in Table 3-6. Changed the 8B/10B reset value for thePCS_RESET_LANE attribute in Table 3-6, Table 3-8, Table 3-10, and Table 3-12. Added reference tothe Virtex-6 FPGA GTH Transceiver Wizard to attribute PCS_RESET_1_LANE, bits [15:2] inTable 3-10. Changed the PCS_RESET_LANE value in step 2 of Enabling 8B/10B Mode, page 85. InTable 3-12, and added reference to the Virtex-6 FPGA GTH Transceiver Wizard to attributePRBS_CFG_LANE, bits [15:4] and PCS_RESET_1_LANE, bits [15:2]; changed the Reserved bits for[13:11] and [10:8] in the PCS_MODE_LANE attribute. In Table 3-13, added reference to the Virtex-6FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0].Added TX Configurable Driver.Chapter 4: Added RX Analog Front End, RX Equalization, and RX CDR. Added reference to theVirtex-6 FPGA GTH Transceiver Wizard to attribute PCS_MISC_CFG_0_LANE, bits [15:12] and[5:0] in Table 4-8, and to attributes PCS_MISC_CFG_0_LANE, bits [15:12] and [5:0],PCS_RESET_1_LANE bits [15:2], and PRBS_CFG_LANE bits [15:4] in Table 4-10. In the FunctionalDescription section of RX Pattern Checker, added paragraph about when the checker is forced intoPRBS31 mode, and added two sentences at the end of the section. Added Table 4-9. Changed the8B/10B reset value for the PCS_RESET_LANE attribute in Table 4-10, Table 4-13, Table 4-16, andTable 4-18. Deleted PRBS checker reference in Description of RXCODEERR in Table 4-12,Table 4-15, Table 4-17, and Table 4-21. In Table 4-13, Table 4-16, Table 4-18, and Table 4-22, changedtransmitter to receiver in the description of RX_FABRIC_WIDTH, and changed the meaning of bitcode 110 for bits [13:11] and [10:8] of the PCS_MODE_LANE attribute to Reserved. In Table 4-13,Table 4-16, and Table 4-18, added reference to the Virtex-6 FPGA GTH Transceiver Wizard toattribute PCS_RESET_1_LANE, bits [15:2]. Changed the PCS_RESET_LANE value in step 2 ofEnabling 8B/10B Mode, page 130. Added 32 and 64 bits to 8B/10B mode in Table 4-19. Added tworows to 8B/10B Mode for 32-bit and 64-bit fabric interface data width in Table 4-20. Revisedmanual adjustment mode settings for the BUFFER_CONFIG_LANE attribute in Table 4-22.Added Chapter 5, Board Design Guidelines.