Xilinx Virtex-6 FPGA User Manual

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Xilinx Virtex-6 FPGA User Manual Manual pdf 44 page image

44 www.xilinx.com Virtex-6 FPGA GTH Transceivers User GuideUG371 (v2.0) February 16, 2010Chapter 2: Shared Transceiver FeaturesPorts and AttributesTable 2-1 defines the reference clock input structure ports for the GTHE1_QUADprimitive.Table 2-2 defines the reference clock input structure ports for the IBUFDS_GTHE1 softwareprimitive.Table 2-3 defines the reference clock input structure attribute for the GTHE1_QUADsoftware primitive.Using the Reference ClockThe reference clock is always used in an AC-coupled mode. The recommended value forthe AC-coupling capacitors is 100 nF. The LVPECL clock must be used to drive thereference clock pins. Refer to DS152, Virtex-6 FPGA Data Sheet: DC and SwitchingCharacteristics for electrical and switching specifications.Table 2-1: Reference Clock Input Structure Ports for the GTHE1_QUAD PrimitivePort Dir Clock Domain DescriptionREFCLK In N/A REFCLK is an external clock driven by theO port of the IBUFDS_GTHE1 softwareprimitive as the reference clock to theGTHE1_QUAD primitive.Table 2-2: Reference Clock Input Structure Ports for the IBUFDS_GTHE1 PrimitivePort Dir Clock Domain DescriptionI In Async This port is the positive input of the referenceclock differential pair.IB In Async This port is the negative input of the referenceclock differential pair.O Out Async This port is the output of the reference clockbuffer connected to the REFCLK port of theGTHE1_QUAD primitive.Table 2-3: Reference Clock Input Structure AttributeAttribute Type DescriptionPLL_CFG1 16-bit Binary This attribute defaults to 16'h8440.[15]: REFCLK termination control (pll_refclk_term_b)AC-coupled mode: 1'b1Reserved: 1'b0[14:0]: ReservedReserved: 15'h0440