Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Contents
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 192UG586 November 30, 2016 www.xilinx.comChapter 1: DDR3 and DDR2 SDRAM Memory Interface SolutionDesign GuidelinesGuidelines for DDR2 and DDR3 SDRAM designs are covered in this section.For general PCB routing guidelines, see Appendix A, General Memory Routing Guidelines.DDR3 SDRAMThis section describes guidelines for DDR3 SDRAM designs, including bank selection, pinallocation, pin assignments, termination, I/O standards, and trace lengths.Design RulesMemory types, memory parts, and data widths are restricted based on the selected FPGA,FPGA speed grade, and the design frequency. The final frequency ranges are subject tocharacterization results.DQS_BYTE_MAPBank and byte laneposition information forthe strobe. See theCK_BYTE_MAP description.This parameter variesbased on the pinout andshould not be changedmanually in generateddesign.See the CK_BYTE_MAP example.DATA0_MAP,DATA1_MAP,DATA2_MAP,DATA3_MAP,DATA4_MAP,DATA5_MAP,DATA6_MAP,DATA7_MAP,DATA8_MAPBank and byte laneposition information forthe data bus. See theADDR_MAP description.This parameter variesbased on the pinout andshould not be changedmanually in generateddesign.See the ADDR_MAP example.MASK0_MAP,MASK1_MAPBank and byte laneposition information forthe data mask. See theADDR_MAP description.This parameter variesbased on the pinout andshould not be changedmanually in generateddesign.See the ADDR_MAP example.Table 1-66: DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters (Cont’d)Parameter Description ExampleSend Feedback |
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