Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 90UG586 November 30, 2016 www.xilinx.comChapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution10. Run implementation flow with the Vivado tool. For details about implementation, seethe Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 7].Note: Similar steps can be followed for the user design using appropriate .dcp and .xdc files.Core ArchitectureThis section describes the architecture of the 7 series FPGAs memory interface solutionscore, providing an overview of the core modules and interfaces.OverviewThe 7 series FPGAs memory interface solutions core is shown in Figure 1-51.X-Ref Target - Figure 1-51Figure 1-51: 7 Series FPGAs Memory Interface Solutionrstclkapp_addrapp_cmdapp_enapp_hi_priapp_wdf_dataapp_wdf_endapp_wdf_maskapp_wdf_wrenapp_rdyapp_rd_dataapp_rd_data_endapp_rd_data_validapp_wdf_rdyapp_sr_reqapp_sr_activeapp_ref_reqapp_ref_ackapp_zq_reqapp_zq_ackddr_ad drddr_baddr_cas_nddr_ckddr_ckeddr_cs_nddr_dmddr_o dtddr_ra s_nddr_reset_nddr we nddr_dqddr_dqs_nddr_dqsUserFPGALogicDDR2/DDR3SDRAMUserInterfaceBlockMemoryControllerPhysicalLayer7 Series FPGAs Memory Interface SolutionUser Interface (1) Physical Interface7 Series FPGAsNative Interface MC/PHY Interfaceddr_ck_nddr_parityIOB1. System clock (sys_clk_p and sys_clk_n/sys_clk_i), Reference clock (clk_ref_p and clk_ref_n/clk_ref_i), and system reset (sys_rst_n) portconnections are not shown in block diagram.Send Feedback |
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