Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 674UG586 November 30, 2016 www.xilinx.comAppendix A: General Memory Routing Guidelines12. For ADDR/CMD/CTRL V TT termination, every four termination resistors should beaccompanied by one 1.0 μF capacitor, physically interleaving among resistors, as shownin Figure A-6.X-Ref Target - Figure A-6Figure A-6: Example of V TT Termination PlacementUG583_c2_17_050614Send Feedback

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Appendix A: General Memory Routing Guidelines

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7 Series

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