Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 621UG586 November 30, 2016 www.xilinx.comChapter 4: LPDDR2 SDRAM Memory Interface SolutionSimilarly, when the wr_data_en signal is asserted, the Memory Controller is processing awrite command request.When NORM ordering mode is enabled, the Memory Controller reorders received requeststo optimize throughput between the FPGA and memory device. The data is returned to theuser design in the order processed, not the order received. The user design can identify thespecific request being processed by monitoring rd_data_addr and wr_data_addr.These fields correspond to the data_buf_addr supplied when the user design submitsthe request to the native interface. Both of these scenarios are depicted in Figure 4-69.The native interface is implemented such that the user design must submit one request ata time and, thus, multiple requests must be submitted in a serial fashion. Similarly, the coremust execute multiple commands to the memory device one at a time. However, due topipelining in the core implementation, read and write requests can be processed in parallelat the native interface.User ZQSee User ZQ for the UI. The feature is identical in the native interface.Customizing the CoreThe 7 series FPGAs memory interface solution supports several configurations for LPDDR2SDRAM devices. The specific configuration is defined by Verilog parameters in the top-levelof the core. As per the OOC flow, none of the parameter values are passed down to the userdesign RTL file from the example design top RTL file. So, any design related parameterchange is not reflected in the user design logic. The MIG tool should be used to regeneratea design when parameters need to be changed. The parameters set by the MIG tool aresummarized in Table 4-25 to Table 4-27.Send Feedback |
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