Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 644UG586 November 30, 2016 www.xilinx.comChapter 5Multicontroller DesignIntroductionThis chapter describes the specifications (including the supported features andunsupported features) and pinout rules for multicontroller designs.The supported and unsupported features are:• Supports up to eight controllers° Multi-interface support includes the combination of all memory interfaces as DDR3SDRAM (Native only), QDR II+ SRAM, and RLDRAM II up to total of eightcontrollers. Multi-interface support with the DDR3 SDRAM AXI interface combinedwith other memory interfaces is not supported.° Multicontroller for DDR3 SDRAM (AXI only) interface is supported up to eightindependent controllers. Multicontroller support combining DDR3 SDRAM Nativeand AXI interface designs is not supported.• Banks selected for one of the controllers are not allowed for other controllers; that is,across the same memory interfaces and different memory interfaces.• Memory options (frequency, data width, etc.) and all other options remain the same asfor single controller options.• Sharing of banks across two different controllers is not allowed.• Rules for all memory interfaces (DDR3 SDRAM, QDR II+ SRAM, and RLDRAM II) remainthe same as for single controller designs.IMPORTANT: Memory Interface Solutions v4.1 only supports the Vivado ® Design Suite. The ISE ®Design Suite is not supported in this version.Send Feedback |
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