Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 458UG586 November 30, 2016 www.xilinx.comChapter 3: RLDRAM II and RLDRAM 3 Memory Interface SolutionsCustomizing the CoreThe RLDRAM II/RLDRAM 3 memory interface solution is customizable to support severalconfigurations. The specific configuration is defined by Verilog parameters in the top-levelof the core. As per the OOC flow, none of the parameter values are passed down to the userdesign RTL file from the example design top RTL file. So, any design related parameterchange is not reflected in the user design logic. The MIG tool should be used to regeneratea design when parameters need to be changed. The parameters are summarized inTable 3-14.X-Ref Target - Figure 3-60Figure 3-60: RLDRAM II Write Calibration WaveformsTable 3-14: RLDRAM II Memory Interface Solution Configurable ParametersParameter Description OptionsCLK_PERIOD Memory clock period (ps). –ADDR_WIDTH Memory address bus width. 18–22RLD_ADDR_WIDTH Physical Memory address bus width when using AddressMultiplexing mode. 11, 18–22BANK_WIDTH Memory bank address bus width. RLDRAM II: 3RLDRAM 3: 4Send Feedback |
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