Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 317UG586 November 30, 2016 www.xilinx.comChapter 2: QDR II+ Memory Interface SolutionCore ArchitectureOverviewFigure 2-38 shows a high-level block diagram of the 7 series FPGA QDR II+ SRAM interfacesolution. This figure shows both the internal FPGA connections to the client interface forinitiating read and write commands, and the external interface to the memory device.X-Ref Target - Figure 2-38Figure 2-38: High-Level Block Diagram of QDR II+ Interface Solution8*BFBB 4'5,,65$0..:56$'%:43K\VLFDO,QWHUIDFH&OLHQW,QWHUIDFHTGUBEZBQTGUBFTBSTGUBFTBQTGUBTFONV\VBUVWUVWBGNFONBZUFONBPHPPPFPBORFNHGLRGHOD\BFWUOBUG\&46HULHV)3*$&4TGUBNBSTGUBNBQTGUBZBQTGUBUBQTGUBVDTGUBGDSSBZUBFPGDSSBZUBDGGUDSSBZUBGDWDDSSBZUBEZBQDSSBUGBFPGDSSBUGBDGGUDSSBUGBYDOLGDSSBUGBGDWDLQLWBFDOLEBFRPSOHWHSend Feedback |
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