Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 631UG586 November 30, 2016 www.xilinx.comChapter 4: LPDDR2 SDRAM Memory Interface SolutionDesign GuidelinesGuidelines for LPDDR2 SDRAM designs are covered in this section.For general PCB routing guidelines, see Appendix A, General Memory Routing Guidelines.LPDDR2 SDRAMThis section describes guidelines for LPDDR2 SDRAM designs, including bank selection, pinallocation, pin assignments, termination, I/O standards, and trace lengths.Design RulesMemory types, memory parts, and data widths are restricted based on the selected FPGA,FPGA speed grade, and the design frequency. The final frequency ranges are subject tocharacterization results.Pin AssignmentsThe MIG tool generates pin assignments for a memory interface based on physical layerrules.Bank and Pin Selection Guides for LPDDR2 DesignsXilinx 7 series FPGAs are designed for very high-performance memory interfaces, andcertain rules must be followed to use the LPDDR2 SDRAM physical layer. Xilinx 7 seriesFPGAs have dedicated logic for each DQS byte group. Four DQS byte groups are available ineach 50-pin bank. Each byte group consists of a clock-capable I/O pair for the DQS and 10associated I/Os.In a typical LPDDR2 configuration, 8 of these 10 I/Os are used for the DQS: one is used forthe data mask (DM), and the remaining one is used for DQS sampling. However, there wouldnot be any physical connect on this pin because it would be internally used to capture theDQS for the phase detector.Xilinx 7 series FPGAs have dedicated clock routing for high-speed synchronization that isrouted vertically within the I/O banks. Thus, LPDDR2 memory interfaces must be arrangedin the banks vertically and not horizontally. In addition, the maximum height is three banks.Send Feedback |
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