Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 575UG586 November 30, 2016 www.xilinx.comChapter 4: LPDDR2 SDRAM Memory Interface SolutionCore ArchitectureThis section describes the architecture of the 7 series FPGAs memory interface solutionscore, providing an overview of the core modules and interfaces.OverviewThe 7 series FPGAs memory interface solutions core is shown in Figure 4-44.User FPGA LogicThe user FPGA logic block shown in Figure 4-44 is any FPGA design that requires to beconnected to an external LPDDR2 SDRAM. The user FPGA logic connects to the MemoryController through the user interface. An example user FPGA logic is provided with the core.X-Ref Target - Figure 4-44Figure 4-44: 7 Series FPGAs Memory Interface Solutionrstclkapp_addrapp_cmdapp_enapp_hi_priapp_wdf_dataapp_wdf_endapp_wdf_maskapp_wdf_wrenapp_rdyapp_rd_dataapp_rd_data_endapp_rd_data_validapp_wdf_rdyapp_sr_reqapp_sr_activeapp_ref_reqapp_ref_ackapp_zq_reqapp_zq_ackddr_caddr_ck_nddr_ckeddr_cs_nddr_dmddr_dqddr_dqs_nddr_dqsUserFPGALogicLPDDR2SDRAMUserInterfaceBlockMemoryControllerPhysicalLayer7 Series FPGAs Memory Interface SolutionUser Interface (1) Physical Interface7 Series FPGAsNative Interface MC/PHY Interfaceddr_ckIOB1. System clock (sys_clk_p and sys_clk_n/sys_clk_i), Reference clock (clk_ref_p and clk_ref_n/clk_ref_i), and system reset (sys_rst_n) portconnections are not shown in block diagram.Send Feedback |
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