Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 380UG586 November 30, 2016 www.xilinx.comChapter 3: RLDRAM II and RLDRAM 3 Memory Interface SolutionsUsing MIG in the Vivado Design SuiteThis section provides the steps to generate the Memory Interface Generator (MIG) IP coreusing the Vivado Design Suite and run implementation.1. Start the Vivado Design Suite (see Figure 3-1).2. To create a new project, click the Create New Project option shown in Figure 3-1 toopen the page as shown in Figure 3-2.X-Ref Target - Figure 3-1Figure 3-1: Vivado Design SuiteSend Feedback

Introduction

Using MIG in the Vivado Design Suite

Synplify Pro Black Box Testing

Core Architecture

Designing with the Core

Interfacing to the Core

Customizing the Core

Design Guidelines

pin assignments

Debugging DDR3/DDR2 Designs

technical support

Debugging QDR II+ SRAM Designs

implementation details

Debugging RLDRAM II and RLDRAM 3 Designs

Appendix A: General Memory Routing Guidelines

Xilinx Resources

Please Read: Important Legal Notices

Xilinx Zynq-7000 User Manual

7 Series

Revision History

Guide Contents

Additional Resources

Overview and Features

Series FPGAs Transceivers Wizard

Implementation

Reference Clock Input Structure

Reference Clock Selection and Distribution

Reset and Initialization

Power Down

Loopback

Dynamic Reconfiguration Port

Digital Monitor

TX Overview

FPGA TX Interface

TX 8B/10B Encoder

running disparity

TX Gearbox

TX Buffer

TX Buffer Bypass

TX Pattern Generator

TX Polarity Control

TX Fabric Clock Output Control

TX Phase Interpolator PPM Controller

TX Configurable Driver

TX Receiver Detect Support for PCI Express Designs

TX Out-of-Band Signaling

RX Overview

RX Analog Front End

RX Out-of-Band Signaling

RX Equalizer

RX Fabric Clock Output Control

RX Margin Analysis

RX Polarity Control

RX Pattern Checker

RX Byte and Word Alignment

enabling comma alignment

activating comma alignment

alignment boundaries

manual alignment

RX 8B/10B Decoder

rx running disparity

special characters

RX Buffer Bypass

RX Elastic Buffer

RX Clock Correction

enabling clock correction

setting clock correction sequences

RX Channel Bonding

enabling channel bonding

setting the maximum skew

RX Gearbox

FPGA RX Interface

Overview

Reference Clock

gtp reference clock checklist

Power Supply and Filtering

SelectIO Usage Guidelines

CPG236 Package Placement Diagram

CSG325 Package Placement Diagram

CLG485 Package Placement Diagram

FGG484 Package Placement Diagram

FGG676 Package Placement Diagram

FBG484 Package Placement Diagram

SBG484 Package Placement Diagram

FBG676 Package Placement Diagram

FFG1156 Package Placement Diagram

Additional Support Resources

DSP48E1 Slice Overview

Features Relative to Prior Generations

Design Recommendations

DSP48E1 Slice Features

Architectural Highlights of the 7 Series FPGA DSP48E1 Slice

DSP48E1 Tile and Interconnect

DSP48E1 Slice Primitive

Simplified DSP48E1 Slice Operation

DSP48E1 Slice Attributes

Input Ports

Output Ports

Embedded Functions

Single Instruction, Multiple Data (SIMD) Mode

Pattern Detect Logic

Designing for Performance

Adder Tree Versus Adder Cascade

Adder Cascade

Connecting DSP48E1 Slices across Columns

DSP48E1 Design Resources

Memory-Mapped I/O Register Application

Zynq-7000