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uPD72256
NEC µPD72257 Preliminary User's Manual
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NEC µPD72257 Preliminary User's Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Chapter 1 Introduction
Block diagrams
Chapter 2 Pin Functions
Ravin-L pin list
Ravin-M pin list
Pull-up resistor pin groups
Ravin-L Pin Functions
Ravin-L pin to signals reference
Ravin-M Pin Functions
Ravin-M pinout options
Ravin-M pin to signals reference
Recommended Connection of unused Pins
Pin States with Respect to Reset
Chapter 3 Memory and Register Map
Ravin-M Memory and Register Map
Chapter 4 System Controller
Functional Overview
Clock Generator
PLL configuration
Main system clock
Resets
PLL restart
Software and Watchdog reset
System Watchdog
Video Input control
Video Output control
Boot Mode Function
System Controller Registers
System Controller registers details
Chapter 5 Host CPU Interface
LBus Interface
LBus-I/F addressing modes
LBus-I/F protocol
LBus-I/F DMA request
ADBus Interface
ADBus-I/F data access
ADBus-I/F principle timing
Address Alignment
Interrupt Controller
AHB Master Status and Interrupts
Host-I/F Registers
Host-I/F registers details
Chapter 6 Video Input (Ravin-M only)
Data Format and Synchronization
RGB data input
Synchronization status information
Start and stop of video capturing
Scaling, Cropping and Storing
Cropping
Scaling
Storing
YUV(4:2:2) to YUV(4:4:4) conversion
YUV(4:4:4) to RGB(888) conversion
Dithering
Framebuffer addressing
Interrupts
Interrupt control
Video Input Registers
Video Input registers details
Chapter 7 Video Output
Colour Formats
Display data output formats
Timing Signals
Synchronization signals
DMA FIFO and Framebuffer Addressing
FIFO watermark
Interrupt sources
Start and Stop of Video Output
Video Output Registers
Video Output registers details
Chapter 8 Drawing Engine
Introduction
Drawing Features
Vector drawing
BitBLT
bilinear filtering
Input and Output Data Formats
Rendering Pipeline
Edge setup linear case
Edge setup quadratic case
Band filter
Clamping unit
Combiner unit
Rasterization optimization
Colourization
Texturing
Blending
Rendering Modes
Performance Counters
Drawing Engine Registers
Control registers details
Colour registers details
Limiter registers details
Texture registers details
Miscellaneous registers details
Chapter 9 External Memory Interface Controller
SDRAM Interface
SDRAM Initialization
SDRAM Refresh Control
Static Memory Interface
Address Decoder
Address adjustment
Memory Controller Power-Down
Memory Controller Registers
Memory Controller registers details
Chapter 10 Register List
Preliminary User's Manual
μPD72256, μPD72257
Graphics Controllers
Hardware
Document No. S19203EE1V3UM00
Date published July 07, 2009
© NEC Electronics 2008
Printed in Germany
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