Table 7-4 Display data output formatsSignalTrue colour modes CLUT modeRGB(666)LCDBPP[2:0] = 101BRGB(565)LCDBPP[2:0] = 110BiRGB(1555)LCDBPP[2:0] = 011BVOnB5 B5 B4 B4VOnB4 B4 B3 B3VOnB3 B3 B2 B2VOnB2 B2 B1 B1VOnB1 B1 B0 B0VOnB0 B0 undefined IVOnG5 G5 G5 G4VOnG4 G4 G4 G3VOnG3 G3 G3 G2VOnG2 G2 G2 G1VOnG1 G1 G1 G0VOnG0 G0 G0 IVOnR5 R5 R4 R4VOnR4 R4 R3 R3VOnR3 R3 R2 R2VOnR2 R2 R1 R1VOnR1 R1 R0 R0VOnR0 R0 undefined I7.3 Timing Signals7.3.1 Display data clock signalThe data output clock, i.e. the pixel clock, VOnCLK is generated in the SystemController's clock generator.The edge of VOnCLK used by the Video Output to output the pixel data can beselected:• VOnLCDTIMING2.IPC = 0: data out with rising VOnCLK edge, datastable at falling edge• VOnLCDTIMING2.IPC = 1: data out with falling VOnCLK edge, datastable at rising edgeVideo Output Chapter 7Preliminary User's Manual S19203EE1V3UM00 193
