5.5 Interrupt ControllerThe Host-I/F interrupt controller handles a total number of 32 interrupt signals,three of which are generated by the Host-I/F itself and the other 29 interrupts aregenerated by other functional blocks.The interrupt controller is operated by means of three registers:• HOSTINTFLAG: shows the status of all active interrupts and is usedto reset INT[15:0]• HOSTINTENAB: provides an enable - or mask - bit for each interrupt• HOSTINTSTAT: shows the status of all active and enabled interruptsThe following diagram shows a functional block chart of the interrupt controlcircuitry.Group A interruptsGroup B interruptsINTIN0HOSTINTFLAGHold/clear circuitEnable/mask circuitHOSTINTENAB HOSTINTSTATINTIN1INTIN2INTIN15INTIN16INTIN17INTIN18Output circuitINTIN0INTIN1INTIN2INTIN15INTIN16INTIN17INTIN18INTIN31HINTINTIN31AHB_UNDERRUNAHB_OVERRUNAHB_ERRINT15INT16INT17INT18INT31INTEN0INTEN1INTEN2INTEN15INTEN16INTEN17INTEN18INTEN31Figure 5-12 Interrupt controllerHOSTINTFLAG The interrupts are grouped in 2 categories:• Group A INT[15:0]An occurence of these interrupts are latched in the circuit of theHOSTINTFLAG register and the assigned interrupt flagHOSTINTFLAG.INTINn is set to 1.For resetting the flag to 0, a 1 must be written to the correspondingbit position.• Group B INT[31:16]An occurence of these interrupts are not latched in the circuit of theHOSTINTFLAG register, but in a register of the interrupt source. Itsassigned interrupt flag HOSTINTFLAG.INTINn only reflects thestatus of the interrupt.Resetting of the flag to 0 must be performed in the concerned registerof the interrupt source.In case the interrupt request signal INTIN[15:0] is asserted while a write to its flagto clear it is taking place simultaneously, the flag set process has priority, thus theflag will not be cleared.Chapter 5 Host CPU Interface140 Preliminary User's Manual S19203EE1V3UM00
