9.3 Static Memory InterfaceStatic memory chipselectsStatic memory can be assigned to the chip select areas MCS0 and MCS1.This section describes the functional details of the Memory Controller as a staticmemory controller. Static memory in this context refers to asynchronous SRAMsand asynchronous nor-flash memories.The Memory Controller supports static memories of various data widths. Itprovides three sets of timing registers MSMTMGRk, with k = 0 to 2, for controllingthe static memory, that allows to set up three different interface timingspecifications. Each chip select area, that is configured for static memory, can beassigned to one of the timing registers MSMTMGRk.The chip select area n is configured for static memory by• MEMSMSKRn.MEMTYPE[2:0] = 001B: static RAM for MCSn• MEMSMSKRn.MEMTYPE[2:0] = 010B: flash for MCSnIf static memory is chosen for a chip select, this chip select needs to be associatedwith one of three timing registers MEMSMTMGRk (k = 0 to 2) in the chip selectmask register for chip select n:• MEMSMSKRn.REGSEL[2:0] = k = 0 to 2: timing register MSMTMGRkassigned to MCSn9.3.1 Static RAM timingIn the following the meaning of the timing parameters of the static RAM interfaceis explained by using timing diagram and explanation of the parameters.Note 1. The internal system clock HCLK is included in the diagrams only forexplanatory purposes and does not reflect the correct timing.2. The byte enable signals MSBEN[3:0] are shown as MSBEN, whichshall depict the concerned MSBEN[3:0] signal of the memoryaccess.3. The index k in the register name MEMSMTMGRk means one of thethree timing register sets k = 0 to 2.Chapter 9 External Memory Interface Controller302 Preliminary User's Manual S19203EE1V3UM00
