Video Output bus locking can be en- or disabled by:• SYSVOCTRL.VOnLOCKEN = 0: bus locking disabled• SYSVOCTRL.VOnLOCKEN = 1: bus locking enabledAfter release of RESET SYSVOCTRL.VOnLOCKEN is set to "0", thus bus lockingis disabled.4.6 Boot Mode FunctionThe boot mode function samples the 12 external pins MODE[11:0] upondeassertion of RESET. These pins, which may have other functions during normaloperation, are to be pulled to either high or low level prior to RESET release.The values of MODE[11:0] are stored in the SYSBOOTMODE register. The bootmode value allows to determine a default configuration during assertion ofRESET.Below table provides an overview of the various MODE[11:0] functions and theirpossible settings.Table 4-3 Settings of MODE[11:0]MODE pin Ravin-L Ravin-MMODE[3:0] set to 0000B pinout options settingsMODE[5:4] PLL and clock divider settings PLL and clock divider settingsMODE6 set to L level set to L levelMODE7 enable (H) / disable (L) SDRAM enable (H) / disable (L) SDRAMMODE8 set to L level set to H levelMODE9 enable (H) / disable (L) IRAM set to L levelMODE10 software application use software application useMODE11 set to L level set to L levelMODE[3:0] Pin configuration (Ravin-M only)MODE[3:0] are stored in SYSBOOTMODE.BOOTMODE[3:0] after RESET releaseand are used to select a certain Ravin-M pinout option.Refer also to the chapter "Pin Functions" and the description of theSYSBOOTMODE register.MODE[5:4] PLL and clock generator configurationsMODE[5:4] are stored in SYSBOOTMODE.BOOTMODE[5:4] after RESET releaseand are used to select one out of two PLL and Clock generator configuration foreach graphics controller type.MODE[5:4] defines the following register's reset values:• SYSPLLCTRL register to set up the PLL parameters and thus the PLLoutput clock frequency fPLLCLKOUT• SYSCLKCTRL.VOxDIV[5:0] and SYSCLKCTRL.BUSDIV[1:0] to setup the main system clock frequency fHCLK and the pixel clocksfVOnCLK of the Video Output interfaces.Chapter 4 System Controller98 Preliminary User's Manual S19203EE1V3UM00
