VSW VBPVOnVSYNCIVS = 0Active linesVOnVSYNCIVS = 1VOnVCPINTLCDVCOMP[1:0] = 11BLCDVCOMP[1:0] = 00BLCDVCOMP[1:0] = 01BLCDVCOMP[1:0] = 10BVFPLPPFigure 7-4 VOnVSYNC timing settingVOnCSYNC If the composite synchronization signal VOnCSYNC is selected to be output viaVOnHSYNC (SYSVOCTRL.CSYNCSELn = 1), the active level of the horizontal andvertical synchronization signals must be set as follows:• VOnCSYNC active at high level ifVOnLCDTIMING2.IVS = VOnLCDTIMING2.IVS.IHS, thus- VOnLCDTIMING2.IHS = VOnLCDTIMING2.IVS = 0or- VOnLCDTIMING2.IHS = VOnLCDTIMING2.IVS = 1• VOnCSYNC active at low level ifVOnLCDTIMING2.IVS ≠ VOnLCDTIMING2.IVS.IHS, thus- VOnLCDTIMING2.IHS = 0 and VOnLCDTIMING2.IVS = 1or- VOnLCDTIMING2.IHS = 1 and VOnLCDTIMING2.IVS = 07.4 DMA FIFO and Framebuffer AddressingIn order to sustain a high pixel data rate to the display, the pixel data fetched fromthe memory is buffered by the DMA FIFO.The FIFO is 32 words deep by 32 bits wide, thus has a capacity of 32 pixels inRGB(666), 64 pixels in RGB(565) and 64 pixels in CLUT(8).If the FIFO fill stage drops below a certain level, the DMA function starts to acquirenew data from the framebuffer for refilling the FIFO.Chapter 7 Video Output196 Preliminary User's Manual S19203EE1V3UM00
