5.3.4 ADBus-I/F principle timing(1) Generation of HADWAITThe wait signal HADWAIT requests the Host CPU to extend the bus timing in casethe ADBus-I/F is still busy transferring the data internally. The Host CPU shouldsample the HADWAIT signal and stretch the access cycle upon demand, until theADBus-I/F indicates ready status by de-assertion of HADWAIT.The wait signal HADWAIT behaves as follows:• It is asserted with the falling edge of HADCS.• It is not released before the falling edge of the HADRD/HADWRstrobe.• The rising edge of the HADRD/HADWR strobe sets HADWAIT againto low level.• The rising edge of the HADCS sets HADWAIT back to high level andcompletes the access cycle.Depending on the access type and especially on the occupation of the internalAHB HADWAIT may be active for some longer time, forcing the Host CPU tostretch the current access.In the following some principle timing diagrams are given.Note The vertical dash lines in the following diagram serve as a kind of grid and do nothave any relation to the real timing of the signals.Chapter 5 Host CPU Interface136 Preliminary User's Manual S19203EE1V3UM00
