Addressand dataFIFOHCLK SDRAMENAHBAHB slave I/FAddress decoderSDR-SDRAM controllerStatic memory controllerRegistersMA[24:0]MD[31:0]MDBA[1:0]MDDQM[3:0]MDCKEMDCLKMDFBCLKMDA10PCMCS1MDRASMDCASMSBEN[3:0]MSWRMSOEMDWEMCS0Figure 9-1 Memory Controller block diagram9.2 SDRAM InterfaceSDRAM chip selects SDRAM can be assigned to the chip select area MCS0. Thus the memory typeselection of MCS1 must not be set to SDRAM(MEMSMSKR1.MEMTYPE[2:0] ≠ 000B).SDRAM feedbackclockIn order to compensate signal delays of the memory bus signals on the off-chipPCB, the data MD[31:0] signals are sampled with the SDRAM feed-back clockMDFBCLK instead of MDCLK for data read accesses. Sampling of the read datasignals MD[31:0] with MDFBCLK applies only if data is read from the externalSDRAM, i.e.• SDRAM is enabled by SDRAMEN = 1• SRAM chip select is not active, i.e. MCS1 = 1In case of SRAM or flash the read data is registered with MDCLK.The feed-back clock MDFBCLK have to be connected externally with MDCLK.Also the read pipe have to be set accordingly. This is ensured by the default value010B of bits 8 to 6 in the SDRAM control register MEMSCTLR.Chapter 9 External Memory Interface Controller294 Preliminary User's Manual S19203EE1V3UM00
