The principle timing of the LBus-I/F is shown in the following diagram.Write dataRead dataLBD[7:0]LBCSLBD[7:0]LBWRLBRDFigure 5-2 LBus-I/F principle timingNote For information concerning the exact timing requirements refer to the PreliminaryData Sheet.5.2.2 LBus-I/F addressing modesThree different addressing modes are provided:(1) Short addressing modeA 24-bit address is composed of a 12-bit offset and a 12-bit address.The upper 12 bit of the address are set up by the dedicated commandeeShortOffs, prior to the short address data transfer command eeShort. Theseupper 12 bit are retained until overwrite with the next eeShortOffs.The eeShort command defines the lower 12 bit of the entire address and initiatesthe data transfer. Thus the short addressing mode allows fast access to a 4 KBdata segment by the 2-byte eeShort command.Since short addressing generates a 24-bit address, the address range is limitedto the first 16 MB of the entire 28-bit address range.The data length can be defined within the eeShort command as byte, half-wordor word.(2) Long addressing modeIn this mode the entire 28-bit address is described in the 4-byte eeLongcommand, which initiates also the data transfer. Long addressing mode allowsrandom access to the entire 28-bit address rangeThe data length can be defined within the eeLong command as byte, half-wordor word.(3) Burst addressing modeChapter 5 Host CPU Interface124 Preliminary User's Manual S19203EE1V3UM00
