5.1 Functional OverviewExternal busses The Host-I/F offers the choice between two asynchronous external interfaces:• LBus-I/F: 8-bit interface without address signalsThe communication via the LBus-I/F uses a kind of protocol totransfer address information and data in a sequentiell manner.• ADBus-I/F: separate address-data busses with 16-bit data bus and21-bit address busThe ADBus-I/F allows the external Host CPU to address all internalcomponents and external memory directly via the 21-bit addressbus.Depending on the chosen pin multiplexer option, derived from the MODE[3:0] pinsat release of reset, the Host-I/F selection signal HIFSEL is generated in the SystemController, that activates the correct Host-I/F.Addresses and data are forwarded internally by the• 32-bit data bus iDATA[31:0]• 28-bit address bus iADDR[27:0]Internal busses The addresses provided by the Host CPU are decoded by an address decoderand mapped to 3 different areas:• Host-I/F register bus for accessing all Host-I/F controller internalregisters• APB: single-master bus with the Host-I/F as the only master of theAPB• AHB: multi-master bus with the Host-I/F as one of several mastersof the AHBWhile the Host-I/F register bus and the APB are exclusively used for accessingregisters, the AHB is used for register accesses and for transfer of the video databetween the Host CPU and the video memory as well as between the internalcomponents.Thus the AHB requires particular attention, since any bus traffic impacts transfertime of the video data and may cause e.g. video data output disruptions, whichmay be visible on the display, due to AHB congestions.Interrupt controller The Host-I/F comprises an interrupt controller, that manages all interrupts andgenerates the single interrupt request signal HINT towards the Host CPU.Chapter 5 Host CPU Interface122 Preliminary User's Manual S19203EE1V3UM00
