4.4 System WatchdogIn case the ADBus Host-I/F is used, a continuous assertion of the ADWAIT signalwould block the Host CPU. The System Watchdog detects such situation andrecovers from a possible stalled system.For this reason the external ADWAIT signal is monitored and in case it is assertedfor more than 325 HCLK clocks the System Watchdog reset WDRESET isasserted.WDRESET executes the same reset functions as a software reset bySYSRESET.SWRESET = 1, in particular it does not stop any clock operations.The System Watchdog function is disabled per default and must be activated bySYSWDCRTL.ADWAITZEN = 1.Caution Note that ADWAIT is asserted also if just ADCS is asserted and not followed byany read or write strobe. Such an irregular bus access could also lead to aWDRESET reset if it lasts too long.4.5 Modules Control FunctionsThe System Controller incorporates facilities to control several functions of othermodules.4.5.1 Internal RAM control (Ravin-L only)Prior using the Ravin-L internal RAM its clock IRAMCLK has to be enabled. Thisis done by• SYSCLKCTRL.IRAMCLKEN = 0: IRAMCLK disabled• SYSCLKCTRL.IRAMCLKEN = 1: IRAMCLK enabledThe default setting of SYSCLKCTRL.IRAMCLKEN is subject to the boot modefunction and depends on the level of the MODE9 pin input at release of RESET:• MODE9 = low level: IRAMCLK disabled per default• MODE9 = high level: IRAMCLK enabled per default4.5.2 SDRAM controlPrior using an external SDRAM the SDRAM clock MDCLK has to be enabled. Thisis done by• SYSCLKCTRL.SDREN = 0: MDCLK disabled• SYSCLKCTRL.SDREN = 1: MDCLK enabledThe default setting of SYSCLKCTRL.SDREN is subject to the boot mode functionand depends on the level of the MODE7 pin input at release of RESET:• MODE7 = low level: MDCLK disabled per default• MODE7 = high level: MDCLK enabled per defaultChapter 4 System Controller94 Preliminary User's Manual S19203EE1V3UM00
