Chapter 5 Host CPU InterfaceRavin-M pinfunctionsThe availability of Host CPU I/F at external pins depend on the selected Ravin-Mpinout option.Table 5-1 Host CPU I/F Ravin-M pinout optionsBus SignalRavin-M pinout option1, 2, 6 3, 7, 9ADBus LBusADBusHADA[20:0] √ –HADD[15:0] √ –HADBEN[1:0] √ –HADWR √ –HADRD √ –HADWAIT √ –HADCS √ –LBusHLBD[7:0] – √HLBWR – √HLBRD – √HLBDRQ – √HLBCS – √Shared HINT √ √√: available; –: not availableRavin-L pin functions The Ravin-L provides only the LBus-I/F pins HLBD[7:0], HLBWR, HLBRD,HLBDRQ, HLBCS and the interrupt pin HINT.Interrupts Following tables define the assignment of the Ravin-M respectively Ravin-Linterrupts.Table 5-2 Ravin-M interrupt assignmentsInterrupt HOSTINTFLAG.INTINnGroup Number Name CauseA0 AHB_UNDERRUN AHB overrun INTIN01 AHB_OVERRUN AHB underrun INTIN12 AHB_ERROR Host-I/F AHB error INTIN23 VO0MBEINT Video Output 0 master bus error INTIN34 VI0AHEINT Video Input 0 bus error INTIN45 VO1MBEINT Video Output 1 master bus error INTIN56 not used — INTIN67 RESINT Reset generated INTIN78 VI0SCLINT Video Input 0 scanline match INTIN89 VI0FFOINT Video Input 0 FIFO overflow error INTIN910 not used — INTIN10Preliminary User's Manual S19203EE1V3UM00 119
