9.1 Functional OverviewFeatures The basic features of the Memory Controller are:• SDRAM and static memory controller (static RAM of NOR flashmemory with shared address/data bus)• 25-bit address bus width MA[24:0]• 32-bit data bus MD[31:0]• Two chip selects:- MCS0: SDRAM or static memory- MCS1: static memory• SDRAM interface:- Single-Data-Rate SDRAM- max. 13 row addresses- max. 13 column addresses- max. 2 bank select addresses- data width: 16-bit, 32-bit- up to 128 MB SDRAM• Static memory interface:- data width: 8-bit, 16-bit, 32-bit- up to 128 MB per chips select- separate timings parameters and bus widths for each staticmemory chip select• SDRAM/static memory parameters configurable via registers• Feedback clock MDFBCLK for data read accesses to compensatePCB propagation times• To support refresh of SDRAM even when static memory is accessed,the SDRAM-IF features an exclusive A10 signal called MDA10PC.External Memory Interface Controller Chapter 9Preliminary User's Manual S19203EE1V3UM00 293
