NXP Semiconductors i.MX 6Dual Reference Manual

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ERR005184Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016NXP Semiconductors 163Description:The digital to analog clock domain transfer of the frequency updates is susceptible to meta-stabilityerrors as the transfer is done through a FIFO. During initial power-up, the FIFO ensures properalignment by delaying the read pointer until the write clock has started. For correct operation ofpointers, it is required that there are five edges of the write clock in two edges of the read clock.When a rate change occurs from Gen1 to Gen2 or vice versa, the clock frequencies switch. Duringthis switching, it is possible (depending upon internal clock tree delay in the PHY digital logic) thatthere are six write clock edges between two clock edges of the read clock. This causes the pointersto move out of sync and for some process/voltage/temperature corners can result in continuouscorrupted reads of frequency update inputs to CDR phase mixer.Once the pointers are misaligned, the condition will persist until the clocks are disabled or anotherphase shift occurs in clock phases as a result of rate change. The end result is the CDR loses lockin L0 state.Projected Impact:Low.Workarounds:From Cold start (LTSSM starts in Detect state):• Disable MAC/LTSSM.• Disable MAC/Gen2 support.• Release MAC/LTSSM.• Wait for MAC to enter L0.• From L0, initiate MAC entry to Gen2 if EP/RC supports Gen2.• Wait 2 ms (LTSSM timeout is 24 ms, PHY lock is ~5 μs in Gen2).• If (MAC/LTSSM.state == Recovery.RcvrLock) && (PHY/rx_valid ==0), then pulse PHY/rx_reset. Transition to Gen2 is stuck.Enter L2 from L0:• Driver receives/requests entry to L2.• Wait 2 ms (LTSSM timeout is 24 ms, PHY lock is ~10 μs in Gen1).• If (MAC/LTSSM.state == Recovery.RcvrLock) && (PHY/rx_valid ==0), then pulse PHY/rx_reset. Transition to Gen1 is stuck.Exit from L2 to L0:• Driver receives/requests exit from L2.• Disable MAC Gen2 support.• Release LTSSM to wake-up from L2.• Wait for entry to L0 and then repeat process of entering Gen2 from cold start case (goingthrough Detect).ERR005184 PCIe: Clock pointers can lose sync during clock rate changes