NXP Semiconductors i.MX 6Dual Reference Manual

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ERR009743Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016NXP Semiconductors 83Description:DBGPRSR.SR, bit [3], is the Sticky Reset status bit. The ARM architecture specifies that theprocessor sets this bit to 1 when the non-debug logic of the processor is in reset state.Because of this erratum, the Cortex-A9 processor sets this bit to 1 when the debug logic of theprocessor is in reset state, instead of when the non-debug logic of the processor is in reset state.Projected Impact:- DBGPRSR.SR might not be set to 1 when it should, when the non-debug logic of the processoris in reset state.- DBGPRSR.SR might be set to 1 when it should not, when the debug logic of the processor is inreset state.In both cases, the DBGPRSR.SR bit value might be corrupted, which might prevent the debuglogic from correctly detecting when the non-debug logic of the processor has been reset.Workarounds:No software workaround available as this erratum is related to a debug feature. Users should notrely on the DBGPRSR.SR bit during the debug session.Proposed Solution:No fix scheduledLinux BSP Status:Software workaround is not implemented because this erratum will never be encountered in normaldevice operation, as this erratum is related to a debug feature.ERR009743 ARM: 799770 - DBGPRSR Sticky Reset status bit is set to 1 by the CPUdebug reset instead of by the CPU non-debug reset