NXP Semiconductors i.MX 6Dual Reference Manual

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ERR009219Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016NXP Semiconductors 91Description:Certain applications require the source clock of the LVDS Display Bridge (LDB) to be modifiedto accommodate various display clock frequency requirements. The clock source can be modifiedby programming an asynchronous clock multiplexer (CCM_CS2CDR[LDB_DIx_CLK_SEL]) insoftware.Asynchronous multiplexers or glitchy multiplexers, enable the clock to switch immediately afterthe multiplexer select is changed. Because both clock sources to the multiplexer are asynchronous,switching the clocks from one source to the other can cause a glitch to be generated, regardless ofthe input clock source. This immediate switch of two asynchronous clock domains can cause theoutput clock to glitch. If the input and output clocks are not gated, this clock glitch can propagateto the logic that follows the clock multiplexer, causing the logic to behave unpredictably.A clock gate has not been implemented after the asynchronous clock multiplexer for theLDB_DI0_IPU clock and LDB_DI1_IPU clocks. Due to the absence of this clock gate on thisLDB_DIx_IPU clock path, a glitch generated when the clock source is switched, can lock up theLDB divider causing a loss of the LDB_DIx_IPU clock under certain conditions.Projected Impact:Switching LDB clock sources on an asynchronous clock multiplexer without gating the input andoutput clock can cause clock glitches to propagate to the logic that follows the clock multiplexers,causing the logic to behave unpredictably. With an ungated input clock, under certain conditionsthe clock divider in the LDB_DIx_IPU clock path can incorrectly lock up. This can therefore causea loss of the LDB_DIx_IPU clock which can result in a blank LVDS display screen in the userapplication.Workarounds:The input and output clocks to the asynchronous clock multiplexer are required to be gated priorto switching the source clock. The recommended software workaround is to shut down the clocksto the asynchronous clock multiplexor (CS2CDR: LDB_DIx_CLK_SEL) by disabling therespective PLLs and PFDs prior to performing the clock switch. After the clock switch isperformed the input and output clocks of the multiplexer are re-enabled. Users must ensure that thePFDs are reset after the respective PLLs are locked. It is recommended to perform the LDB clockswitch early in the boot process to minimize the clocking impact.Please refer to Engineering Bulletin EB821 : LDB Clock Switch Procedure and i.MX6Asynchronous Clock Switching Guidelines for further details on the issue and recommendedsoftware workaround procedure.ERR009219 CCM: Asynchronous clock switching can cause unpredictablebehavior [i.MX 6Dual/6Quad Only]