NXP Semiconductors i.MX 6Dual Reference Manual

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ERR003725Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/201628 NXP SemiconductorsDescription:The ISB is implemented as a branch in the Cortex-A9 micro-architecture. This implies that events0x0C (software change of PC) and 0x0D (immediate branch) are asserted when an ISB occurs. Thisis not compliant with the ARM architecture.Projected Impact:The count of events 0x0C and 0x0D are not 100% precise when using the Performance Monitorcounters, due to the ISB being counted in addition to the real software changes to PC (for 0x0C)and immediate branches (0x0D).The erratum also causes the corresponding PMUEVENT bits to toggle in case an ISB is executed.• PMUEVENT[13] relates to event 0x0C• PMUEVENT[14] relates to event 0x0DWorkarounds:Count ISB instructions along with event 0x90. The user should subtract this ISB count from theresults obtained in events 0x0C and 0x0D, to obtain the precise count of software change of PC(0x0C) and immediate branches (0x0D).Proposed Solution:No fix scheduledLinux BSP Status:Software workaround is not needed because this erratum will not be encountered in normal deviceoperation.The Freescale Linux BSP does not support this optional profiling feature. Users may addsupport for this profiling feature as required, but should ensure the multiple errata impacting theARM PMU are considered especially for multi-core usage.ERR003725 ARM: 725631—ISB is counted in Performance Monitor events 0x0Cand 0x0D