NXP Semiconductors i.MX 6Dual Reference Manual

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ERR003720Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/201622 NXP SemiconductorsDescription:In an MPCore configuration with two or more processors working in SMP mode with maintenanceoperation broadcast enabled, if a processor is interrupted while executing an ICIALLUISoperation, and performs another broadcast maintenance operation during its Interrupt ServiceRoutine, then this second operation might not be executed on other processors in the cluster.Conditions:The erratum requires an MPCore configuration with two or more CPUs working in SMP mode.One processor has interrupts enabled, and Cache and TLB maintenance broadcast enabled too(ACTLR.FW=1’b1). This processor executes an ICIALLUIS (invalidates all instruction cachesInner Shareable to Point of Unification). This instruction is executed on the processor, and alsobroadcast to other processors in the MPCore cluster. The processor then receives an interrupt (IRQor FIQ), which interrupts the ICIALLUIS operation.During the Interrupt Service Routine, the processor executes any other Cache or TLB maintenanceoperation which is also broadcast to other processors in the MPCore cluster. If the other processorsin the cluster receive this second maintenance operation before having completed the firstICIALLUIS operation, then the erratum occurs, as the other processors will not execute the secondmaintenance operation. This is because there is no “stacking” mechanism for acknowledgeanswers between the processors, so that the acknowledge request sent to signify the completion ofthe ICIALLUIS will be interpreted by the originating processor as an acknowledge for the secondmaintenance operation.Projected Impact:Due to the erratum, the processor might end up with corrupted entries in the Cache or in the TLB,leading to possible failures in the system.Workarounds:A software workaround is available for this erratum that involves setting bit[11] in theundocumented Diagnostic Control register, placed in CP15 c15 0 c0 1.This bit can be written in Secure state only, with the following Read/Modify/Write code sequence:MRC p15,0,rt,c15,c0,1ORR rt,rt,#0x800MCR p15,0,rt,c15,c0,1When it is set, this bit prevents CP15 maintenance operations to be interrupted.Using this software workaround is not expected to cause any visible impact on the system.Proposed Solution:No fix scheduledERR003720 ARM/MP: 751472—An interrupted ICIALLUIS operation may preventthe completion of a following broadcast operation