NXP Semiconductors i.MX 6Dual Reference Manual

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ERR007573Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016174 NXP SemiconductorsDescription:When the core's LTSSM is in Recovery.RcvLock or Recovery.RcvCfg, and it receives TS Orderedsets, it does not check whether the link and lane numbers of the received TS Ordered Sets matchwhat is being transmitted on those same lanes.Scenario Setup:Core is in link state "Recovery.RcvLock" or "Recovery.RcvCfg" and receives TS Ordered Setswith link and lane number not matching what is being transmitted on those same Lanes.The absence of link and lane number match checks in Recovery.RcvrLock and Recovery.RcvrCfgstates only affects single lane configurations (CX_NL = 1). All configurations are not affect, asstated in the Impacted Configurations section above.Projected Impact:The core moves from Recovery.RcvLock to Recovery.RcvCfg or from Recovery.RcvCfg toRecovery.Idle and LTSSM misses the condition of link and lane number match and moves to thenext state without robustness.Workarounds:NoneProposed Solution:No fix scheduled.Linux BSP Status:Software workaround cannot be implemented to mask or workaround this SoC issue. This erratumwill result in impacted or reduced functionality as described above.ERR007573 PCIe: Link and lane number-match not checked in recovery(9000569433)