ERR007006Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016NXP Semiconductors 73Description:A processor which continuously executes a short loop containing a DMB instruction might preventa CP15 operation broadcast by another processor from making further progress, thus causing adenial of service.The erratum requires the following conditions:• Two or more processors are working in SMP mode (ACTLR.SMP=1)• One of the processors continuously executes a short loop containing at least one DMBinstruction.• Another processor executes a CP15 maintenance operation that is broadcast. This requires thatthis processor has enabled the broadcasting of CP15 operations (ACTLR.FW=1)For the erratum to occur, the short loop containing the DMB instruction must meet all of thefollowing additional conditions:• No more than 10 instructions other than the DMB are executed between each DMB• No nonconditional Load or Store, or conditional Load or Store which pass the condition codecheck, are executed between each DMBWhen all the conditions for the erratum are met, the short loop creates a continuous stream of DMBinstructions. This might cause a denial of service, by preventing the processor executing the shortloop from executing the received broadcast CP15 operation. As a result, the processor thatoriginally executed the broadcast CP15 operation is stalled until the execution of the loop isinterrupted.Note that because the process issuing the CP15 broadcast operation cannot complete operation, itcannot enter any debug mode, and cannot take any interrupt. If the processor executing the shortloop also cannot be interrupted—for example if it has disabled its interrupts—or if no interruptsare routed to this processor, this erratum might cause a system livelock.Projected Impact:The erratum might create performance issues, or in the worst case it might cause a system livelock,if the processor executing the DMB is in an infinite loop that cannot be interrupted.Workarounds:This erratum can be worked around by setting bit[4] of the undocumented Diagnostic Controlregister to 1. This register is encoded as CP15 c15 0 c0 1.This bit can be written in Secure state only, with the following Read/Modify/Write code sequence:MRC p15,0,rt,c15,c0,1ORR rt,rt,#0x10MCR p15,0,rt,c15,c0,1When it is set, this bit causes the DMB instruction to be decoded and executed like a DSB.Using this software workaround is not expected to have any impact on the overall performance ofthe processor on a typical code base.ERR007006 ARM/MP:794072-- Short loop including a DMB instruction mightcause a denial of service