NXP Semiconductors i.MX 6Dual Reference Manual

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ERR007557Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016172 NXP SemiconductorsDescription:16-bit, 32-bit, or 64-bit PIPE I/F (CX_NB >= 2)Gen1/Gen2 Mode (CX_GEN3_MODE = 2)When running at Gen1 or Gen2 speed, if the valid core data width on a lane is 2s (two symbols) orhigher and the Extended Synch bit is set in the Link Control Register, then the core sends one extraFTS (4097 instead of 4096) when exiting L0s.Scenario Setup:1. Set the Extended Synch bit in the Link Control Register.2. Enable L0s ASPM by setting Link Control Register bit 0 to 1.3. Bring the link to L0 at Gen1 or Gen2 speed and leave the link idle.4. The controller goes to L0s after an L0s entry latency timeout.5. Initiate a TLP transmission.6. The controller wakes up and sends 4097 FTS.Projected Impact:There is no impact on a link in normal operating mode because the Extended Synch bit is used forexternal Link monitoring tools. It is not used in an operational PCIe Link.When the core transmits FTS, the remote partner is in Rx_L0s.FTS. The next state for the remotepartner is L0 if a SKP is received. If the Extended Synch bit is set, the core will transmit at least 12separate SKP Ordered Sets during the 4096 FTSs transmitted. The PCIe Specification says thatwhen the extended synch bit is set, the Receiver N_FTS timeout must be adjusted to no shorter than40* [2048] * UI (2048 FTSs) and no longer than 40* [4096] * UI (4096 FTSs). The fact that thecore sends 4097 FTSs instead of 4096 will not matter, because according to the requirement above,the remote partner will timeout before the extra FTS is sent.Workarounds:NoneProposed Solution:No fix scheduled.Linux BSP Status:No software workaround can be implemented to mask or workaround this erratum. This erratumwill result in impacted or reduced functionality as described above.ERR007557 PCIe: Extra FTS sent when Extended Synch bit is set (9000588281)