ERR005175Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016NXP Semiconductors 55Description:Preload Data (PLD) instructions prefetch and allocate any data marked as Write-Back (eitherWrite-Allocate or Non-Write-Allocate, Shared or Non-Shared), regardless of the processorconfiguration settings, including the Data Cache Enable bit value.Projected Impact:Due to this erratum, unexpected memory cacheability aliasing is created which might result invarious data consistency issues.In practice, this erratum is not expected to cause any significant issue. The Data Cache is expectedto be enabled as soon as possible in most systems, and not dynamically modified. So, only boot-upcode would possibly be impacted by this erratum, but such code is usually carefully controlled andnot expected to contain any PLD instruction while Data Cache is not enabled.Workarounds:In the case where a system is impacted by this erratum, a software workaround is available whichconsists in setting bit [20] in the undocumented Control register, which is placed in CP15 c15 0 c01.This bit needs to be written with the following Read/Modify/Write code sequence:MRC p15,0,r0,c15,c0,1ORR r0,r0,#0x00100000MCR p15,0,r0,c15,c0,1Setting this bit causes all PLD instructions to be treated as NOPs, with the consequence that codesequences usually using the PLDs, such as the memcpy() routine, might suffer from a visibleperformance drop. So, if this workaround is applied, ARM strongly recommends restricting itsusage to periods of time where the Data Cache is disabled.Proposed Solution:No fix scheduledLinux BSP Status:Software workaround not implemented in Linux BSP. Functionality or mode of operation in whichthe erratum may manifest itself is not used. The BSP does not dynamically enable/disable datacache during run-time and thus avoids the PLD instruction with the data cache off.ERR005175 ARM/MP: 771221—PLD instructions may allocate data in the DataCache regardless of the Cache Enable bit value