NXP Semiconductors i.MX 6Dual Reference Manual

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ERR003724Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/201626 NXP SemiconductorsDescription:A microTLB entry might be corrupted following an ASID switch, possibly corrupting subsequentMMU translations.The erratum requires execution of an explicit memory access, which might be speculative. Thismemory access misses in the TLB and cause a translation table walk. The erratum occurs when thetranslation table walk starts before the ASID switch code sequence, but completes after the ASIDswitch code sequence. In this case, a new entry is allocated in the microTLB for the TLB entry forthis translation table walk, but corresponding to the old ASID. Because the microTLB does notrecord the ASID value, the new MMU translation, which should happen with the new ASIDfollowing the ASID switch, might hit this stale microTLB entry and become corrupted.Note that there is no Trustzone Security risk because the Security state of the access is held in themicroTLB, and cannot be corrupted.Projected Impact:The errata might cause MMU translation corruptions.Workarounds:The workaround for this erratum involves adding a DSB in the ASID switch code sequence. TheARM architecture only mandates ISB before and after the ASID switch. Adding a DSB prior to theASID switch ensures that the Page Table Walk completes prior to the ASID change, so that no staleentry can be allocated in the micro-TLB.The examples in the ARM Architecture Reference Manual for synchronizing the change in theASID and TTBR need to be changed as follows:The sequence:Change ASID to 0ISBChange Translation Table Base RegisterISBChange ASID to new valuebecomesDSBChange ASID to 0ISBChange Translation Table Base RegisterISBDSBChange ASID to new valuethe sequence:Change Translation Table Base Register to the global-only mappingsISBChange ASID to new valueERR003724 ARM: 754322—Possible faulty MMU translations following an ASIDswitch