Virtex-4 FPGA Configuration User Guide www.xilinx.com 19UG071 (v1.12) June 2, 2017Bitstream Loading (Steps 4-7)Rthe device to upcoming configuration data and aligns the configuration data with theinternal configuration logic. Any data on the configuration input pins prior tosynchronization is ignored.Synchronization is transparent to most users because all configuration bitstreams (.bitfiles) generated by the Xilinx ISE® Bitstream Generator (BitGen) software include thesynchronization word. Table 1-5 shows signals relating to synchronization.Check Device ID (Step 5)Once the device is synchronized, a device ID check must pass before the configuration dataframes can be loaded. This prevents an attempted configuration with a bitstream that isformatted for a different device.For example, the device ID check should prevent an XC4VLX15 from being configuredwith an XC4VLX80 bitstream.The device ID check is built into the bitstream, making this step transparent to mostdesigners. Figure 1-7 shows the relative position of the device ID check, Table 1-6 showsthe Virtex-4 device IDs, and Table 1-7 shows the signals relating to the device ID check. Thedevice ID check is performed through commands in the bitstream to the configurationlogic, not through the JTAG IDCODE register in this case.Table 1-5: Signals Relating to SynchronizationSignal Name Type Access DescriptionDALIGN Status Only available through theSelectMAP interface during anABORT. (See “ConfigurationAbort Sequence Description,”page 49.)Indicates whether deviceis synchronized.Figure 1-7: Check Device ID (Step 5)Table 1-6: Virtex-4 Device ID CodesDevice IDCODE Device IDCODE Device IDCODEXC4VLX15 01658093 XC4VFX12 01E58093XC4VLX25 0167C093 XC4VSX25 02068093 XC4VFX20 01E64093XC4VLX40 016A4093 XC4VSX35 02088093 XC4VFX40 01E8C093(1)XC4VLX60 016B4093 XC4VSX55 020B0093 XC4VFX60 01EB4093XC4VLX80 016D8093XC4VLX100 01700093 XC4VFX100 01EE4093XC4VLX160 01718093 XC4VFX140 01F14093DevicePower-UpSample ModePins Synchronization Device IDCheck CRC CheckClearConfigurationMemoryStartupSequenceLoadConfigurationDataStart Finishug071_07_122105BitstreamLoadingSteps1 2 3 4 5 6 7 8
