Xilinx Virtex-4 Configuration User Manual

Also see for Virtex-4 RocketIO: User guide User guide

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Xilinx Virtex-4 Configuration User Manual Manual pdf 85 page image

Virtex-4 FPGA Configuration User Guide www.xilinx.com 85UG071 (v1.12) June 2, 2017Dynamic Reconfiguration of Functional Blocks (DRP)Ras a percentage of the clock. Just as in legacy mode, PSDONE indicates completion of thephase shift. If DLL_PHASE_SHIFT_LOCK_BY1 = 0, then the lower three bits of phase shiftvalue are ignored, because it works on eight tabs as a unit.Phase shift overflow does not toggle in the Direct Mode if the end of the delay line isreached.It is recommended that the same clock be used for DCLK and PSCLK. Although thePSDONE pin is a function of the PSCLK domain, the data written to the DRP is in theDCLK domain. If this cannot be done, then the following two scenarios should beconsidered:1. Connect DCLK, but not PSCLK. PSDONE is not asserted. The phase shift value isexecuted, although there is no indication when it is completed.2. Connect PSCLK and DCLK to different sources. PSDONE is in the PSCLK domainand can be asynchronous to DCLK.Setting a direct phase shift value:1. If the CLKOUT_PHASE_SHIFT was not set to DIRECT, then write 00Dh (DI) toDADDR address 56h. (DRP should not be used to change configuration memory otherthan phase shift value.)2. Write the desired tab value 0-3FFh (DI) (0-1023 tabs) to DADDR 55h.3. Write to DADDR 11h to start the phase shift. (Data on DI does not matter.)4. PSDONE asserts for one PSCLK cycle to indicate that the phase shift is done.ICAP - Internal Configuration Access PortThe Internal Configuration Access Port (ICAP) allows access to configuration data in thesame manner as SelectMAP. ICAP has the same interface signaling as SelectMAP otherthan the data bus, which is separated into read and write data buses. ICAP has a chip-select signal (CS), a read-write control signal (RD), a clock (CLK), a write data bus (DIN),and a read data bus (OUT). ICAP can be configured to two different data bus widths, 8 bitsor 32 bits. When the 8-bit ICAP interface is used, the data is byte-reversed like SelectMAP.When the 32-bit interface is used, the data is not reversed, which is the same asSelectMAP32.The ICAP interface can be used to perform readback operations or partial reconfiguration.When using ICAP for partial reconfiguration, the user must avoid changing the logic orinterconnect which the ICAP is itself connected to. ICAP can also be used to read or writeto the configuration registers, such as the STAT, CTL, or FAR registers. See “AccessingConfiguration Registers through the SelectMAP Interface” for details.There are two ICAP sites in Virtex-4 devices: TOP and BOTTOM. The implementation hasthe two interfaces share the same underlying logic. The only difference between them istheir location on the chip and the interconnect to which they can be connected. The twointerfaces can never be active at the same time. The default site for a single ICAP is the TOPsite, because the TOP site is active after configuration by default. If both sites are used, theTOP site must be activated first before switching to the BOTTOM site. The process ofswitching between the two sites is as follows:1. Synchronize the current interface (if it's not already synched).2. Write bit 30 of the MASK register with a 1.3. Write bit 30 of the CTL register with a 1 if switching to the BOTTOM site or a 0 ifswitching to the TOP site.4. Write the DESYNCH command to the CMD register.5. Synchronize the new ICAP site.