Xilinx Virtex-4 Configuration User Manual

Also see for Virtex-4 RocketIO: User guide User guide

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Xilinx Virtex-4 Configuration User Manual Manual pdf 2 page image

Virtex-4 FPGA Configuration User Guide www.xilinx.com UG071 (v1.12) June 2, 2017The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To themaximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALLWARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OFMERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whetherin contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arisingunder, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, orconsequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any actionbrought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products aresubject to the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed athttp://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole riskand liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed athttp://www.xilinx.com/legal.htm#tos.© 2004–2017 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinxin the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. Allother trademarks are the property of their respective owners.Revision HistoryThe following table shows the revision history for this document.RVersion Revision08/02/04 1.0 Initial Xilinx release. Printed Handbook version.09/10/04 1.1 Chapters 11, 12, and 13 in the printed handbook are now Chapters 1, 2, and 3 in thisguide. Chapter 14 in the printed handbook is now Chapter 6 in this guide. There are noweight chapters in this guide.08/08/05 1.2 System Monitor functions are not supported in Virtex-4 devices, removed references.General typographical edits for correctness and clarity. Edited Table 1-1, Table 1-4,Figure 1-11, Table 2-4, and Figure 2-11 to add information on Slave SelectMAP32 mode.Removed the Virtex-4 bitstream length tables in favor of the exact numbers reported inthe ISE BitGen tool. Edited Table 1-3 and removed the Power-Up Timing table toconsolidate data in the Virtex-4 FPGA Data Sheet. Edited Figure 1-11. Removed theDynamic Reconfiguration Timing table to consolidate data in the Virtex-4 FPGAData Sheet.08/16/05 1.3 Due to a documentation error, all configuration I/O notations have been changed fromLVTTL to LVCMOS.