Virtex-4 FPGA Configuration User Guide www.xilinx.com 89UG071 (v1.12) June 2, 2017Configuration Control LogicRType 2 PacketThe Type 2 packet, which must follow a Type 1 packet, is used to write long blocks. Noaddress is presented here because it uses the previous Type 1 packet address. The headersection is always a 32-bit word.Following the Type 2 packet header is the Type 2 Data section, which contains the numberof 32-bit words specified by the word count portion of the header. See Table 7-4.Configuration RegistersAll bitstream commands are executed by reading or writing to the configuration registers.Table 7-5 summarizes these registers. A detailed explanation of selected registers follows.Table 7-2: Type 1 Packet Header FormatHeaderType Opcode Register Address Reserved Word Count[31:29] [28:27] [26:13] [12:11] [10:0]001 xx RRRRRRRRRxxxxx RR xxxxxxxxxxxNotes:1. "R" means the bit is not used and reserved for future use.Table 7-3: Opcode FormatOpcode Function00 NOP01 Read10 Write11 ReservedTable 7-4: Type 2 Packet HeaderHeaderType Opcode Word Count[31:29] [28:27] [26:0]010 RR xxxxxxxxxxxxxxxxxxxxxxxxxxTable 7-5: Configuration RegistersReg. Name Read/Write Address DescriptionCRC Read/Write 00000 CRC registerFAR Read/Write 00001 Frame Address RegisterFDRI Write 00010 Frame Data Register, Input (write configuration data)FDRO Read 00011 Frame Data Register, Output register (readconfiguration data)CMD Read/Write 00100 Command RegisterCTL Read/Write 00101 Control Register
