Virtex-4 FPGA Configuration User Guide www.xilinx.com 41UG071 (v1.12) June 2, 2017SelectMAP Configuration InterfaceRSingle Device SelectMAP ConfigurationThe simplest way to configure a single device in SelectMAP mode is to connect it directlyto a parallel configuration PROM as shown in Figure 2-12. In this arrangement, the deviceis set for Master SelectMAP mode, and the RDWR_B and CS_B pins are tied to Ground forcontinuous data loading (see “SelectMAP Data Loading”).Notes relevant to Figure 2-12:1. The DONE pin is by default an open-drain output requiring an external pull-upresistor. A 330Ω pull-up resistor is recommended. In this arrangement, the activeDONE driver can be enabled, eliminating the need for an external pull-up resistor.2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrequired.3. The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.4. The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serialPROMs can be cascaded to increase the overall configuration storage capacity.5. The .bit file must be reformatted into a PROM file before it can be stored on the serialPROM. Refer to the “Generating PROM Files” section.6. On XC17V00 devices, the reset polarity is programmable. RESET should be set foractive Low when using an XC17V00 device in this setup.7. The Xilinx PROM must be set for parallel mode. Note that this mode is not availablefor all devices.8. When configuring a Virtex-4 device in SelectMAP mode from a Xilinx configurationPROM, the RDWR_B and CS_B signals can be tied Low (see “SelectMAP DataLoading”).9. The BUSY signal does not need to be monitored for this setup and can be leftunconnected (see “SelectMAP Data Loading”).10. The CCLK net requires Thevenin parallel termination. See “Board Layout forConfiguration Clock (CCLK),” page 34.11. The CCLK pin is an output and an input.Figure 2-12: Single Device Master SelectMAP Configurationug071_22_073007Virtex-4MasterSelectMAPD[0:7]PROGRAM_BCCLKDONEINIT_BDATA[0:7]CCLKCFCERDWR_BCS_BRESET/OEXilinxSerial PROM(2)(1)M2M1M0(10)(10)
