Xilinx Virtex-4 Configuration User Manual

Also see for Virtex-4 RocketIO: User guide User guide

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Xilinx Virtex-4 Configuration User Manual Manual pdf 84 page image

84 www.xilinx.com Virtex-4 FPGA Configuration User GuideUG071 (v1.12) June 2, 2017Chapter 6: Reconfiguration Techniques RIf the M or D values are dynamically charged, then in some cases, the frequency modemust also be charged to comply with the specifications in the data sheet. For theDFS_FREQUENCY_MODE DRP address, 41h must be read and bit 6 (DI[5]) is then set to:• 0 for low frequency mode• 1 for high frequency modeAll other bits must remain unchanged.For the DLL_FREQUENCY_MODE DRP address, 58h must be read and bits 7 and 8(DI[7:6) are then set to:• 0 for low frequency mode• 1 for high frequency modeAgain, all other bits must be left undisturbed.Dynamic Phase Shifting Through the DRP in Direct ModeIn addition to the phase shift modes already available in Virtex-II and Virtex-II Pro devices,the Virtex-4 FPGA has implemented a Direct Phase Shift Mode (DPSM). This allows theuser to control the phase-shift delay line elements (tabs) directly. The DPSM can beaccessed through either the standard Phase Shift (PS) interface or the DRP. If the DCMattribute CLKOUT_PHASE_SHIFT is set to DIRECT, then the PS interface is in direct modeand controls individual taps. The initial tap value is 0 delay line elements. All four PSinterface signals act identically to the legacy-phase shift mode, thus allowing increment ordecrement of the tabs. The delay line element is inserted at the CLKIN path. CLKIN leadsCLKFB mode when more delay line elements are inserted until the delay elements areequal to one clock period, at which time the dynamic phase starts over again.If DLL_PHASE_SHIFT_LOCK_BY1 = 1, each increment/decrement changes one tab. If 0,each increment/decrement changes eight tabs.The DRP interface allows to the user to directly set an initial phase-shift value to a specifiednumber of taps. After RESET, the phase-shift delay line has no elements inserted. A valuebetween 0 and 3FFh (0-1023 taps) can be written to the DRP, then setting the tap targetvalue in the DCM. A write to a specific address of the DRP then initiates the adjustmentcycles necessary to set the proper delay value in the DPS. The DCM requires fewer clockcycles to achieve the final value than in the other modes, where a phase shift is expressedTable 6-3: Divider SettingsDADDR[15:0] DEC DI[15:0] Function52h 0000 0000h (0000000000000000) N/A52h 0001 0001h (0000000000000001) Divide by 252h 0002 0002h (0000000000000010) Divide by 352h 0003 0003h (0000000000000011) Divide by 452h 0004 0004h (0000000000000100) Divide by 5••••••••••••52h 0030 001Eh (0000000000011110) Divide by 3152h 0031 001Fh (0000000000011111) Divide by 32