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Xilinx Virtex-4 RocketIO manuals

Virtex-4 RocketIO first page preview

Virtex-4 RocketIO

Brand: Xilinx | Category: Transceiver
Table of contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. MGT Features
  11. User Guide Organization
  12. Related Information
  13. Port and Attribute Names
  14. Typographical
  15. basic architecture and capabilities
  16. Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram
  17. configuring the rocketio mgt
  18. Attributes
  19. Byte Mapping
  20. Clock Distribution
  21. Figure 2-1: MGT Column Clocking
  22. GT11CLK_MGT and Reference Clock Routing
  23. MGT Clock Ports and Attributes
  24. Common Reference Clock Use Models
  25. Fabric Clocks
  26. PMA Transmit Clocks
  27. PMA Receive Clocks
  28. RX and TX PLL Voltage-Controlled Oscillator (VCO) Operating Frequency
  29. Figure 2-6: Transmitter and Receiver Line Rates
  30. Figure 2-7: PCS Receive Clocking Domains and Datapaths
  31. PMA Configurations
  32. Figure 2-9: Low-Latency Clocking
  33. Figure 2-10: DCM Clocking
  34. Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2)
  35. Figure 2-11 (Cont'd): Receive Clocking Decision Flow (Page 2 of 2)
  36. Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2)
  37. Figure 2-12 (Cont'd): Transmit Clocking Decision Flow (Page 2 of 2)
  38. RXCLKSTABLE and TXCLKSTABLE
  39. Resets
  40. TXRESET
  41. CRC Reset
  42. Figure 2-14: Flow Chart of TX Reset Sequence Where TX Buffer Is Used
  43. Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used
  44. Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed
  45. and tx_align_err Is Not Used
  46. Figure 2-18: Resetting the Transmitter Where TX Buffer Is Bypassed
  47. Figure 2-19: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Used
  48. Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used
  49. Figure 2-21: Resetting the Receiver in Analog CDR Mode Where RX Buffer Is Used
  50. Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed
  51. Reset Considerations
  52. RX Reset Sequence Background
  53. Top-Level Architecture
  54. Fabric Interface Synchronicity
  55. Bus Interface
  56. Internal Bus Width Configuration
  57. Fabric Interface Functionality
  58. Figure 3-5: Fabric Interface Timing
  59. PCS Bypass Byte Mapping
  60. B/10B Encoding/Decoding
  61. Encoder
  62. txchardispval and txchardispmode
  63. TXCHARISK
  64. Decoder
  65. RXCHARISK and RXRUNDISP
  66. RXNOTINTABLE
  67. Non-Standard Running Disparity Example
  68. Summary
  69. Bit / 10-Bit Alignment
  70. Figure 3-13: 6-Bit Alignment Mux Position
  71. SONET Alignment
  72. Figure 3-16: SONET Alignment Sequence (2-Byte External Data Interface Width)
  73. Alignment Status
  74. RXSLIDE
  75. Clock Correction Sequences
  76. CLK_COR_SEQ_LEN Attributes
  77. Determining Correct CLK_COR_MIN_LAT and CLK_COR_MAX_LAT
  78. Channel Bonding
  79. cccb_arbitrator_disable attribute
  80. Disable Channel Bonding
  81. Figure 3-20: Daisy-Chained Transceiver CHBONDI/CHBONDO Buses
  82. RX Fabric Interface and Channel Bonding
  83. Event Indication
  84. Digital Receiver
  85. Figure 3-23: Digital Receiver Example
  86. Clocking in Buffered Mode
  87. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2
  88. Serial I/O Description
  89. Emphasis
  90. Figure 4-3: Effect of 3-Tap Pre-Emphasis on a Pulse Signal
  91. Figure 4-4: TX with Minimal Pre-Emphasis
  92. Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis
  93. Figure 4-6: TX with Maximal Pre-Emphasis
  94. Differential Receiver
  95. Receiver Lock Control
  96. Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer
  97. Special Analog Functions
  98. POWERDOWN
  99. RXDCCOUPLE
  100. Figure 5-1: 32-bit CRC Inputs and Outputs
  101. Functionality
  102. Figure 5-2: 64-Bit to 32-Bit Core Interface
  103. handling end-of-packet residue
  104. Bit Example
  106. Bit Transmission, Hold CRC, and Residue of 8-Bit Example
  107. Implementation
  109. Physical Requirements
  110. Figure 6-1: MGT Tile Power and Serial I/O Pins
  111. Power Supply Requirements
  112. Voltage Regulation
  113. Figure 6-4: Power Filtering Network for One MGT Tile
  114. Powering Unused MGTs
  115. Figure 6-6: Optimizing Filtering for an MGT Column
  116. Reference Clock
  117. Termination
  118. AC and DC Coupling
  119. Figure 6-11: AC-Coupled Serial Link
  120. SelectIO-to-MGT Crosstalk
  121. Routing Serial Traces
  122. Differential Trace Design
  123. Figure 6-15: Obstacle Route Geometry
  124. Model Considerations
  125. HSPICE
  126. Out-of-Band (OOB) Signaling
  127. Simulating in Verilog
  128. Phase-Locked Loop
  129. MGT Ports that Cannot Be Simulated
  130. MGT Package Pins
  131. Introduction
  132. Receiver
  133. Transmitter
  134. PCS Data Path Latency
  135. Ports and Attributes
  138. Use Models
  139. TX Low Latency Buffered Mode with Channel Deskew
  141. Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A
  142. Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B
  143. Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C
  144. Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D
  145. Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E
  146. Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F
  147. Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G
  148. Skew
  149. TX Low Latency Buffer Bypass Mode
  151. Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A
  153. Timing
  154. Worst-Case TX Skew Estimation
  155. synchronization clock = grefclk, txphasesel = false
  156. TX Skew Estimation Examples
  157. RX Latency
  159. Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A
  160. Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B
  161. Reset
  162. RX Low Latency Buffer Bypass Mode
  163. Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A
  164. Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B
  166. RXSYNC
  167. XAUI
  169. Powering the RocketIO MGTs
  170. Clock Traces
  171. How Fast is Fast
  172. Relative Permittivity
  173. Traces
  174. Figure 10-1: Differential Edge-Coupled Centered Stripline
  175. Trace Routing
  176. Cable
  177. excess capacitance and inductance
  178. Figure 11-1: TDR Signature of Shunt Capacitance
  179. Figure 11-4: 2D Field Solver Analysis of 5 Mil Trace and 28 Mil Pad
  180. Figure 11-6: Ansoft HFSS Model of Capacitor with a Pad Clear-Out
  181. on Log (Frequency) Scale
  182. Differential Vias
  183. Figure 11-11: Differential GSSG Via in 16-layer PCB from Pins L11 and L6
  184. Microstrip/Stripline Bends
  185. Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs
  186. Figure 11-16: Simulated Phase Response of 45 Degree Bends with Jog-Outs
  187. BGA Packages
  189. Summary of Guidelines
  190. Figure 12-1: Differential Via Dimensions
  191. Figure 12-2: BGA Escape Design Example
  192. Figure 12-3: Via Structures for BGA Adjacent SIO
  193. Figure 12-4: XENPAK70 Connector Design Example
  194. Figure 12-5: SMT XFP Connector Design Example
  195. Figure 12-7: Tyco Z-PACK HM-Zd Press-Fit Connector
  196. Figure 12-9: Tyco Z-PACK HM-Zd Press-Fit Connector Design Example
  197. Figure 12-10: SMT DC Blocking Capacitor Design Example
  199. Figure A-1: RocketIO Multi-Gigabit Transceiver Block Diagram
  200. Input Setup/Hold Times Relative to Clock
  201. Figure A-2: MGT Timing Relative to Clock Edge
  202. interface description
  203. Memory Map
  204. receiver sample phase adjustment
  205. Primary Differences
  206. Clocking
  207. Serial Rate Support
  208. Board Guidelines
  209. Other Minor Differences
  210. Loopback
  211. RXSTATUS Bus
Virtex-4 RocketIO first page preview

Virtex-4 RocketIO

Brand: Xilinx | Category: Motherboard
Table of contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Guide Contents
  6. Additional Resources
  7. Online Document
  8. Introduction
  9. Setup (Steps 1-3)
  10. Clear Configuration Memory (Step 2, Initialization)
  11. Sample Mode Pins (Step 3)
  12. Bitstream Loading (Steps 4-7)
  13. Check Device ID (Step 5)
  14. Load Configuration Data Frames (Step 6)
  15. Startup (Step 8)
  16. Bitstream Encryption
  17. Creating an Encrypted Bitstream
  18. Bitstream Encryption and Internal Configuration Access Port (ICAP)
  19. Serial Configuration Interface
  20. Clocking Serial Configuration Data
  21. Slave Serial Configuration
  22. Configuring a Serial Daisy Chain with a Microprocessor or CPLD
  23. Mixed Serial Daisy Chains
  24. Ganged Serial Configuration
  25. Startup Sequencing (GTS)
  26. PROM Files for Ganged Serial Configuration
  27. Single Device SelectMAP Configuration
  28. Multiple Device SelectMAP Configuration
  29. Ganged SelectMAP
  30. SelectMAP Data Loading
  31. Continuous SelectMAP Data Loading
  32. Non-Continuous SelectMAP Data Loading
  33. SelectMAP ABORT
  34. Readback Abort Sequence Description
  35. Resuming Configuration or Readback After an Abort
  36. SelectMAP Data Ordering
  37. Configuration Data Files
  38. Generating PROM Files
  39. PROM Files for SelectMAP Configuration
  41. TAP Controller
  42. Boundary-Scan Architecture
  43. Instruction Register
  44. BYPASS Register
  45. Configuration Register (Boundary-Scan)
  46. Configuring Through Boundary-Scan
  47. Reconfiguring through Boundary-Scan
  48. Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1532
  49. Clocking Startup and Shutdown Sequences (JTAG)
  50. Configuration Flows Using JTAG
  51. Using Frame ECC Logic
  52. Using the User Access Register
  53. Dynamic Reconfiguration of Functional Blocks (DRP)
  54. FPGA Fabric Port Definition
  55. DRP DCM Implementation
  56. Dynamic Phase Shifting Through the DRP in Direct Mode
  57. ICAP - Internal Configuration Access Port
  58. Configuration Memory Frames
  59. Configuration Control Logic
  60. Type 2 Packet
  61. Command Register (CMD)
  62. Control Register (CTL)
  63. Frame Address Register (FAR)
  64. Status Register (STAT)
  65. Configuration Options Register (COR)
  66. Bitstream Composition
  67. Preparing a Design for Readback
  68. Readback Command Sequences
  69. Configuration Register Read Procedure (SelectMAP)
  70. Configuration Memory Read Procedure (SelectMAP)
  71. Accessing Configuration Registers through the JTAG Interface
  72. Configuration Memory Read Procedure (1149.1 JTAG)
  73. Configuration Memory Read Procedure (1532 JTAG)
  74. Verifying Readback Data
  75. Readback Capture
Virtex-4 RocketIO first page preview

Virtex-4 RocketIO

Brand: Xilinx | Category: IP Access Controllers
Table of contents
  1. Revision History
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Guide Contents
  6. Conventions
  7. Ethernet MAC Overview
  8. Features
  9. Architecture Overview
  10. Ethernet MAC Primitive
  11. Ethernet MAC Signal Descriptions
  12. Clock Signals
  13. Host Interface Signals
  14. Reset and CLIENTEMAC#DCMLOCKED Signals
  15. Tie-Off Pins
  16. Management Data Input/Output (MDIO) Interface Signals
  17. RocketIO Multi-Gigabit Transceiver Signals
  18. Client Interface
  19. Transmit (TX) Client – 8-bit Wide Interface
  20. Transmit (TX) Client – 16-bit Wide Interface
  21. Receive (RX) Client – 8-bit Wide Interface
  22. Receive (RX) Client – 16-bit Wide Interface
  23. Address Filtering
  24. Flow Control Block
  25. Statistics Vector
  26. Host Interface
  27. Host Clock Frequency
  28. Address Filter Registers
  29. Using the DCR Bus as the Host Bus
  30. Description of Ethernet MAC Register Access through the DCR Bus
  31. Address Code
  32. MDIO Interface
  33. MDIO Implementation in the EMAC
  34. Accessing MDIO via the EMAC Host Interface
  35. Media Independent Interface (MII)
  36. MII Clock Management
  37. MII Signals
  38. Gigabit Media Independent Interface (GMII) Signals
  39. GMII Clock Management
  40. Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only)
  41. GMII Signals
  42. RGMII
  43. Gb/s RGMII Clock Management
  44. Tri-Mode RGMII v2.0
  45. Tri-Mode RGMII v1.3
  46. RGMII Signals
  47. Serial Gigabit Media Independent Interface (SGMII)
  48. SGMII Interface
  49. SGMII Clock Management
  50. SGMII Signals
  51. Management Registers
  52. BASE-X PCS/PMA
  53. Shim
  54. PCS/PMA Signals
  55. Clock Frequency Support
  56. Transmit Clocking Scheme
  57. Receive Clocking Scheme
  58. Auto-Negotiation Interrupt
  59. Auto-Negotiation Link Timer
  60. Simulation Models
  61. Pinout Guidelines
  62. Interfacing to the Processor DCR
  63. Interfacing to an FPGA Fabric-Based Statistics Block
  64. When the Ethernet MAC Is Implemented with the DCR Bus
  65. Accessing the Ethernet MAC from the CORE Generator tool
  66. Timing Parameters
  67. Clock to Output Delays
  68. Timing Diagram and Timing Parameter Tables
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