52 www.xilinx.com Virtex-4 FPGA Configuration User GuideUG071 (v1.12) June 2, 2017Chapter 2: Configuration Interfaces RSelectMAP Data OrderingIn many cases, SelectMAP configuration is driven by a user application residing on amicroprocessor, CPLD, or in some cases another FPGA. In these applications, it isimportant to understand how the data ordering in the configuration data file correspondsto the data ordering expected by the FPGA.In SelectMAP 8-bit mode, configuration data is loaded at one byte per CCLK, with the MSBof each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs frommany other devices. This can be a source of confusion when designing customconfiguration solutions. Table 2-6 shows how to load the hexadecimal value 0xABCD intothe SelectMAP data bus.Some applications can accommodate the non-conventional data ordering withoutdifficulty. For other applications, it can be more convenient for the source configurationdata file to be byte-swapped, meaning that the bits in each byte of the data stream arereversed. For these applications, the Xilinx PROM file generation software can generatebyte-swapped PROM files (see “Configuration Data Files”).In SelectMAP 32-bit mode, configuring the data order is straight D0 = LSB and D31 = MSB.Table 2-6: Bit Ordering for SelectMAP 8-bit ModeCCLK Cycle HexEquivalent D0 D1 D2 D3 D4 D5 D6 D71 0xAB 1 0 1 0 1 0 1 12 0xCD 1 1 0 0 1 1 0 1Notes:1. D[0:7] represent the SelectMAP 8-bit mode data pins.
