Xilinx Virtex-4 Configuration User Manual

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Xilinx Virtex-4 Configuration User Manual Manual pdf 21 page image

Virtex-4 FPGA Configuration User Guide www.xilinx.com 21UG071 (v1.12) June 2, 2017Startup (Step 8)Rconfiguration data frames, causing incorrect design behavior, or even damaging thedevice.If a CRC error occurs during configuration, the device must be resynchronized andreconfigured. In serial modes, the device can only be resynchronized by pulsing thePROGRAM_B pin and restarting the configuration process from the beginning. InSelectMAP modes, either the PROGRAM_B pin can be pulsed Low or an ABORT sequencecan be initiated (see “SelectMAP Configuration Interface” in Chapter 2).Virtex-4 devices use a 32-bit CRC check. The CRC check is designed to catch errors intransmitting the configuration bitstream. There is a scenario where errors in transmittingthe configuration bitstream can be missed by the CRC check:Certain clocking errors, such as double-clocking, can cause loss of synchronizationbetween the 32-bit bitstream packets and the configuration logic. Oncesynchronization is lost, any subsequent commands are not understood, including thecommand to check the CRC. In this situation, configuration fails with DONE Low andINIT_B High.Virtex-4 configuration uses a standard CRC32C checksum algorithm. The CRC32Cpolynomial is:Startup (Step 8)After the configuration frames are loaded, the bitstream instructs the device to enter thestartup sequence. The startup sequence is controlled by an 8-phase (phases 0–7) sequentialstate machine. The startup sequencer performs the tasks outlined in Table 1-8.The specific order of startup events (except for EOS assertion) is user-programmablethrough BitGen options (refer to the Development System Reference Guide). Table 1-8 showsthe general sequence of events, although the specific phase for each of these startup eventsis user-programmable (EOS is always asserted in the last phase). Refer to Chapter 2,x32 x28 x27 x26 x25 x23 x22 x20 x19 x18 x14 x13 x11 x10 x9 x8 x6 1+ + + + + + + + + + + + + + + + +Figure 1-10: Start-Up Sequence (Step 8)Table 1-8: User-Selectable Cycle of Startup EventsPhase Event1– 6 Wait for DCMs to Lock (optional)1– 6 Wait for DCI to Match (optional)1– 6 Assert GWE (Global Write Enable), allowing RAMs and flip-flops to change state1– 6 Negate GTS (Global 3-State), activating I/O1– 6 Release DONE pin7 Assert EOS (End Of Startup)DevicePower-UpSample ModePins Synchronization Device IDCheck CRC CheckClearConfigurationMemoryStartupSequenceLoadConfigurationDataStart Finishug071_10_122105BitstreamLoadingSteps1 2 3 4 5 6 7 8