Xilinx Virtex-4 Configuration User Manual

Also see for Virtex-4 RocketIO: User guide User guide

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Xilinx Virtex-4 Configuration User Manual Manual pdf 75 page image

Virtex-4 FPGA Configuration User Guide www.xilinx.com 75UG071 (v1.12) June 2, 2017RChapter 4Frame ECC LogicUsing Frame ECC LogicConfigurable memory is highly reliable, however to provide extra reliability, the solutionexplained in this chapter has been provided.The Frame error correction code (ECC) logic of the Virtex®-4 FPGA is designed to detectsingle- or double-bit errors in configuration frame data. It uses SECDED (Hamming code)parity values based on the frame data generated by BitGen. During readback, the FrameECC logic calculates a syndrome value using all the bits in the frame, including the ECCbits. If the bits have not changed from the original programmed values, then the syndromeare all 0s. If a single bit has changed, including any of the ECC bits, then the location of thebit is indicated by syndrome bits 10:0 and syndrome bit 11 is 1. If two bits have changed,then syndrome bit 11 is 0 and the remaining bits is non-zero and meaningless. If more thantwo bits have changed then the syndrome is indeterminate. The error output of the block isasserted if one or two bits have changed, indicating that action needs to be taken.To use the Frame ECC logic, FRAME_ECC _VIRTEX4 must be instantiated in the user'sdesign, and readback must be performed through SelectMAP, JTAG, or ICAP. At the end ofeach frame of readback, the syndrome_valid signal is asserted for one cycle of the readbackclock (CCLK, TCK, or ICAP_CLK). The number of cycles required to read back a framevaries with the interface used. Refer to Chapter 8, “Readback and ConfigurationVerification,” for further information.The FRAME_ECC_VIRTEX4 logic does not repair changed bits; this requires a user design.The design must be able to store at least one frame of data, or be able to fetch originalframes of data for reload. A single frame is 1,312 bits. Following is an example of a simplerepair implementation:1. A frame is read out through ICAP and stored in block RAM. The frame address mustbe generated as each frame is read.2. If an error is indicated by the error output of the FRAME_ECC block, then the readbackis halted and the syndrome value saved. If bit 11 is 0, then the whole frame must berestored. If bit 11 is 1, then bits 10:0 are used to locate the error bit in the saved frame,and the bit inverted.3. The repaired frame is then written back into the frame address generated in step 1.4. Readback then begins again with the next frame address.The syndrome bits S[10:0] are derived from the Hamming parity bits, while S[11] is derivedfrom the overall parity bit. The syndrome bit is interpreted as follows:S[11] = 0, S[10:0] = 0: no error.S[11] = 1, S[10:0] ≠ 0: single bit (SED) error; S[10:0] denotes location of bit topatch (indirectly).