CHAPTER 3: INSTALLATION DIRECT INPUT AND OUTPUT COMMUNICATIONSC70 CAPACITOR BANK PROTECTION AND CONTROL SYSTEM – INSTRUCTION MANUAL 3-293Figure 3-31: G.703 timing selection switch settingTable 3-4: G.703 timing selections3.4.3.3 G.703 octet timingIf octet timing is enabled (ON), this 8 kHz signal is asserted during the violation of bit 8 (LSB) necessary for connecting tohigher order systems. When C70s are connected back-to-back, octet timing is disabled (OFF).3.4.3.4 G.703 timing modesThere are two timing modes for the G.703 module: internal timing mode and loop timing mode (default).• Internal Timing Mode — The system clock is generated internally. Therefore, set the G.703 timing selection to internaltiming mode for back-to-back (UR-to-UR) connections. For back-to-back connections, set octet timing (S1 = OFF) andtiming mode to internal timing (S5 = ON and S6 = OFF).• Loop Timing Mode — The system clock is derived from the received line signal. Therefore, set the G.703 timingselection to loop timing mode for connections to higher order systems. For connection to a higher order system (UR-to-multiplexer, factory defaults), set to octet timing (S1 = ON) and set timing mode to loop timing (S5 = OFF and S6 =OFF).The switch settings for the internal and loop timing modes are shown.Switches FunctionS1 OFF → octet timing disabledON → octet timing 8 kHzS5 and S6 S5 = OFF and S6 = OFF → loop timing modeS5 = ON and S6 = OFF → internal timing modeS5 = OFF and S6 = ON → minimum remote loopback modeS5 = ON and S6 = ON → dual loopback modeCover screwTop coverBottom coverEjector/inserter clipEjector/inserter clipTiming selectionswitchesChannel 1Channel 2FRONTREAR831774A3.CDR
