3-44 C70 CAPACITOR BANK PROTECTION AND CONTROL SYSTEM – INSTRUCTION MANUALDIRECT INPUT AND OUTPUT COMMUNICATIONS CHAPTER 3: INSTALLATION3addition, the send timing outputs of data module 1 are also paralleled to the terminal timing inputs of data module 2. Byusing this configuration, the timing for both data modules and both UR RS422 channels is derived from a single clocksource. As a result, data sampling for both of the UR RS422 channels is synchronized via the send timing leads on datamodule 1, shown as follows. If the terminal timing feature is not available or this type of connection is not wanted, theG.703 interface is a viable option that does not impose timing restrictions.Figure 3-47: Timing configuration for RS422 two-channel, three-terminal applicationData module 1 provides timing to the C70 RS422 interface via the ST(A) and ST(B) outputs. Data module 1 also providestiming to data module 2 TT(A) and TT(B) inputs via the ST(A) and AT(B) outputs. The data module pin numbers have beenomitted in the figure because they vary by manufacturer.3.4.4.3 Transmit timingThe RS422 interface accepts one clock input for transmit timing. It is important that the rising edge of the 64 kHz transmittiming clock of the multiplexer interface is sampling the data in the center of the transmit data window. Therefore, it isimportant to confirm clock and data transitions to ensure proper system operation. For example, the following figureshows the positive edge of the Tx clock in the center of the Tx data bit.
