101Chapter 3 CPU FunctionsUser’s Manual U16580EE3V1UD003.4.4 Memory mapAreas are reserved in V850E/PH2 as shown in Figure 3-16. Each mode is specified by the MODE0 toMODE2 pins.Figure 3-16: Memory Map ofμPD70F3187Notes: 1. By setting the PMCAL, PMCAH, PMCDL, PMCDH, PMCCS, PMCCT, and PMCCD portmode control registers to control mode, this area can be used as external memory area.2. Accessing addresses 3FFF000H to 3FFFFFFH is prohibited. Specify addresses FFFF000Hto FFFFFFFH to access the on-chip peripheral I/O.3. The operation is not guaranteed if an access-prohibited area is accessed.xFFFFFFFH On-chip peripheralI/O areaInternal RAM areaOn-chip peripheralI/O areaInternal RAM areaOn-chip peripheralI/O areaInternal RAM areaAccess prohibitedNote 1External memoryareaInternal ROM areaExternal memoryareaInternal ROM areaExternal memoryareaSingle-chip mode 0 Single-chip mode 1 ROMless modeProgram area(64 MB)1 MB1 MB4 KBx0200000Hx01FFFFFHx0100000Hx00FFFFFHx0000000H32 KBxFFFF000HxFFFEFFFHxFFF0000HxFFEFFFFHOn-chip peripheralI/O area mirrorNote 2x3FF0000Hx3FEFFFFHAccess prohibitedNote 3xFFF8000HxFFF7FFFHx3FF8000Hx3FF7FFFH Internal RAM areamirrorx3FFF000Hx3FFEFFFHx4000000Hx3FFFFFFHAccess prohibitedNote 2On-chip peripheralI/O area mirrorNote 2Access prohibitedNote 3Internal RAM areamirrorOn-chip peripheralI/O area mirrorNote 2Access prohibitedNote 3Internal RAM areamirrorAccess prohibitedNote 1 Access prohibitedNote 1Access prohibitedNote 1
