480Chapter 11 16-bit Timer/Event Counter TUser’s Manual U16580EE3V1UD0011.5 Basic Operation11.5.1 Basic counter operationThis section describes the basic operation of the counter. For details, refer to chapter 11.6 Operationin Each Mode.(1) Counter start operation(a) Encoder compare modeThe count operation is controlled by the phases of pins TENCTn0 and TENCTn1.When TTnCE = 0 and TTnECC = 0, the counter is initialized by the TTnTCW register and thecount operation is started. (The setting value of the TTnTCW register is loaded to the counter atthe timing when TTnCE changes from 0 to 1.)(b) Triangular wave PWM MODEThe counter starts counting from initial value FFFFH.It counts up FFFFH, 0000H, 0001H, 0002H, 0003H…Following count up operation, the counter counts down upon a match with the TTnCCR0 register.(c) Modes other than the aboveThe counter starts counting from initial value FFFFH.It counts up FFFFH, 0000H, 0001H, 0002H, 0003H…(2) Counter clear operationThere are the following five counter clear causes.• Clear through match between counter value and compare setting value.• Capture and clear through capture input• Counter clear through encoder clear input (TECRTn pin)• Counter clear through match with clear condition level• Clear through clear signal input (TTnSYCI) for synchronization function during slave operationRemark: n = 0, 1
