256Chapter 8 Clock GeneratorUser’s Manual U16580EE3V1UD008.3 Power Save Control8.3.1 OverviewThe power save function of V850E/PH2 supports the HALT mode only. In this mode, the clock generator(oscillator and PLL synthesizer) continues to operate, but the CPU’s operation clock stops. Since thesupply of clocks to on-chip peripheral functions other than the CPU continues,operation continues. The power consumption of the overall system can be reduced by intermittentoperation that is achieved due to a combination of HALT mode and normal operation mode.The system is switched to HALT mode by a specific instruction (the HALT instruction).Figure 8-2 shows the operation of the clock generator in normal operation mode and HALT mode.Figure 8-2: Power Save Mode State Transition DiagramNotes: 1. Non-maskable interrupt request signal (NMI) or unmasked maskable interrupt requestsignal.2. The oscillation stabilization time is necessary after release of reset because the PLL isinitialized by a reset. The stabilization time is determined by default.Note 1Normal operation mode HALT modeSet HALT modeWait for stabilization ofoscillation and PLLRESET pin inputInterrupt requestNote 2
